# MCP6N11-010E

**Microchip Tech** · Operational Amplifier · SOIC-8

MCP6N11-010E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VFG | input | Analog feedback input, the inverting input of the second stage, a high-impedance CMOS input with low bias current to which RF and RG connect. |
| 2 | VIM | input | Inverting analog input, a high-impedance CMOS input with low bias currents. |
| 3 | VIP | input | Non-inverting analog input, a high-impedance CMOS input with low bias currents. |
| 4 | VSS | power_in | Negative power supply, connected to ground in single-supply operation; VDD must be 1.8V to 5.5V above VSS and other pins must stay between VSS and VDD. |
| 5 | VREF | power_in | Analog reference input, the non-inverting input of the second stage that shifts VOUT to its desired range, a high-impedance CMOS input with low bias current. |
| 6 | VOUT | output | Low-impedance analog output representing VDM (VIP minus VIM) with gain GDM and shifted by VREF, with RF connected to this pin. |
| 7 | VDD | power_in | Positive power supply, 1.8V to 5.5V above VSS, which requires bypass capacitors. |
| 8 | EN/CAL | input | Schmitt-triggered CMOS enable and VOS calibration input; driving it low places the part in low power mode with output high-Z, and driving it high runs offset calibration before the output reconnects to VOUT. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Operational Amplifier/Comparator |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage, Calibrated | VOS | -0.5 |  | 0.5 | mV |  | 3 |
| Power Supply Rejection Ratio | PSRR | 81 | 102 |  | dB |  | 3 |
| Common Mode Rejection Ratio | CMRR | 79 | 107 |  | dB | VCM = VIVL to VIVH, VDD = 1.8V | 4 |
| Common Mode Rejection Ratio | CMRR | 81 | 114 |  | dB | VCM = VIVL to VIVH, VDD = 5.5V | 4 |
| Common Mode Non-Linearity | INLCM | -125 | 6 | 125 | ppm | VCM = VIVL to VIVH, VDM = 0V, VDD = 1.8V (Note 7) | 4 |
| Common Mode Non-Linearity | INLCM | -50 | 2 | 50 | ppm | VCM = VIVL to VIVH, VDM = 0V, VDD = 5.5V (Note 7) | 4 |
| Differential Gain Error | gE | -1 | 0.13 | 1 | % | VDM = VDML to VDMH, VREF = (VDD -GDMVDM)/2 | 5 |
| Differential Non-Linearity | INLDM | -2000 | 100 | 2000 | ppm |  | 5 |
| DC Open-Loop Gain | AOL | 78 | 104 |  | dB | VDD = 1.8V, VOUT = 0.2V to 1.6V | 5 |
| DC Open-Loop Gain | AOL | 90 | 114 |  | dB | VDD = 5.5V, VOUT = 0.2V to 5.3V | 5 |
| Supply Voltage | VDD | 1.8 |  | 5.5 | V | all | 5 |
| Quiescent Current per Amplifier | IQ | 0.5 | 0.8 | 1.1 | mA | IO = 0 | 5 |
| POR Trip Voltage | VPRL | 1.1 | 1.4 |  | V |  | 5 |
| POR Trip Voltage | VPRH |  | 1.4 | 1.7 | V |  | 5 |
| GND Current | ISS | -7 | -2.5 |  | µA | EN/CAL = 0V, VDD = 5.5V | 7 |
| EN/CAL Low to Amplifier Output High-Z Turn-off Time | tOFF |  | 3 | 10 | µs | EN/CAL = 0.2VDD to VOUT = 0.1(VDD/2), VDMGDM = 1 V, VL = 0V | 7 |
| EN/CAL High to Amplifier Output On Time | tON | 12 | 20 | 28 | ms | EN/CAL = 0.8VDD to VOUT = 0.9(VDD/2), VDMGDM = 1 V, VL = 0V | 7 |
| EN/CAL Low to EN/CAL High low time | tENLH | 100 |  |  | µs | Minimum time before externally releasing EN/CAL (Note 1) | 7 |
| VDD ↑ to Output On | tPLH | 140 | 250 | 360 | ms | VL = 0V, VDD = 0V to VPRH + 0.1V step, 90% of VOUT change | 7 |
| Operating Temperature Range | TA | -40 |  | 125 | °C | (Note 1) | 7 |
| Specified Temperature Range | TA | -40 |  | 125 | °C |  | 7 |
| Storage Temperature Range | TA | -65 |  | 150 | °C |  | 7 |
| Thermal Resistance, 8L-SOIC | θJA |  | 150 |  | °C/W |  | 7 |
| Current at Input Pins |  | -2 |  | 2 | mA |  | 3 |
| Current at Output and Supply Pins |  | -30 |  | 30 | mA |  | 3 |
| Max. Junction Temperature |  |  |  | 150 | °C |  | 3 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | Package: MNY = 2×3 TDFN, 8-lead * SN = Plastic SOIC (150mil Body), 8-lead | 47 |

## CAD (KiCad official)

- Symbol: `MCP6N11-010E`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `mcp6n11-010e-etched.step` / `mcp6n11-010e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp6n11-010e.step` / `mcp6n11-010e.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/mcp6n11-010e-datasheet.pdf) (50 pp, sha256 `b08e0d74003c4ec2`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mcp6n11-010e-datasheet.pdf)