component
MCP6C02T-020E
Public Made by Adomby adom
Microchip Tech Current Sense Amplifiers, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
MCP6C02T-020E
Microchip Tech · Current Sense Amplifiers · SOT-23-6
MCP6C02T-020E from Microchip Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | The analog output pin is a low-impedance voltage source, normally between VSS and VDD. |
| 2 | VSS | power_in | Negative power supply, connected to ground in a single positive supply configuration; it needs good bypass capacitors and must be tied to the exposed pad. |
| 3 | VIP | input | Noninverting high-impedance input treated as the common-mode voltage, normally VSS + 3V to VSS + 65V, and also the high-voltage supply pin that triggers the HV POR; it needs a bypass capacitor (e.g., 10 nF) and a limited edge rate so the ESD diodes do not clamp. |
| 4 | VIM | input | Inverting high-impedance CMOS input with low input bias current, designed to operate near the VIP voltage, with VDM = VIP - VIM as the input signal. |
| 5 | VREF | power_in | High-impedance CMOS analog output reference voltage set to a DC level that shifts VOUT, and whose dynamic response helps reject supply glitches. |
| 6 | VDD | power_in | Positive low-side power supply, normally VSS + 2.0V to VSS + 5.5V, which triggers the LV POR and needs good bypass capacitors. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOT-23-6 |
| Category | Amplifiers/Comparators |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Low supply voltage VDD, specified minimum (LV POR on) | VDDL | 2 | V | All; VDD ↑ (LV POR on) | 5 | ||
| Low supply voltage VDD, operating minimum | VDDL | 1.7 | V | 5 | |||
| Supply voltage VDD, specified maximum | VDDH | 5.5 | V | 5 | |||
| Supply voltage VDD, operating maximum | VDDH | 5.5 | V | 5 | |||
| Common-mode input VIP, specified minimum (HV POR on) | VIPL | 3 | V | VIP ↑ (HV POR on) | 5 | ||
| Common-mode input VIP, operating minimum (HV POR on) | VIPL | 2.8 | V | VIP ↑ (HV POR on) | 5 | ||
| VIP falling POR threshold, specified minimum | VIPLD | 2.8 | V | VIP ↓ (HV POR on) | 5 | ||
| VIP falling POR threshold, operating minimum | VIPLD | 2.6 | V | VIP ↓ (HV POR on) | 5 | ||
| Common-mode input VIP, specified maximum | VIPH | 65 | V | 5 | |||
| Common-mode input VIP, operating maximum | VIPH | 68 | V | 5 | |||
| VREF, specified minimum | VRL | 0 | V | All | 6 | ||
| VREF, operating minimum | VRL | 0 | V | 6 | |||
| VOUT minimum (specified, at RL = 1kΩ) | VOL | 0.06 | V | Note 5: VOL and VOH at RL = 1kΩ | 6 | ||
| Input offset voltage VOS (GDM = 20) | VOS | -16 | 1.9 | 16 | μV | GDM = 20; Input Offset (VIP = VIM); Note 2 | 7 |
| VOS linear drift TC1 (GDM = 20, E-Temp) | TC1 | -90 | 10 | 90 | nV/°C | GDM = 20; TA = -40°C to +125°C, for E-Temp parts (Note 2, Note 3) | 7 |
| Power supply rejection ratio (GDM = 20) | PSRR | 109 | 134 | dB | GDM = 20; VDD = 2.0V to 5.5V | 7 | |
| VIP input bias current | IBP | 120 | 170 | 215 | μA | VDD = 2.0V to 5.5V | 7 |
| VIP voltage range low (rising) | VIPL | 2.4 | 3 | V | VIP ↑ | 8 | |
| VIP voltage range low (falling POR threshold) | VIPLD | 2.15 | 2.8 | V | VIP ↓ | 8 | |
| VIP voltage range high | VIPH | 65 | V | 8 | |||
| Common-mode rejection ratio (GDM = 20) | CMRR | 132 | 159 | dB | GDM = 20; VDD = 2.0V to 5.5V, VIP = 3V to 65V | 8 | |
| Reference voltage VREF lower limit | VRL | 0 | V | All; See Section 5.1.8, Setting the Voltage at VREF | 8 | ||
| Differential gain error gE (GDM = 20) | gE | -1.6 | 0.1 | 1.6 | % | VDD = 5.5V, VREF = 2.75V, GDMVDM = -2.65V to 2.65V | 8 |
| Minimum output voltage swing VOL (at RL = 1kΩ) | VOL | 20 | 60 | mV | VDD = 5.5V, VREF = 0V, VDM = -0.5V/GDM, RL = 1kΩ | 9 | |
| Maximum output voltage swing VDD, VOH (at RL = 1kΩ) | VDD, VOH | 40 | 130 | mV | VDD = 5.5V, VREF = 4.25V, VDM = 1.75V/GDM, RL = 1kΩ | 9 | |
| LV POR trip voltage, turn-off (VDD ↓) | VPLL | 1.05 | 1.35 | V | LV POR turns off (VDD ↓), VL = 0V, VIP = 3V, VREF = 0V | 10 | |
| LV POR trip voltage, turn-on (VDD ↑) | VPLH | 1.45 | 1.7 | V | LV POR turns on (VDD ↑), VL = 0V, VIP = 3V, VREF = 0V | 10 | |
| HV POR trip voltage, turn-off (VIP ↓) | VPHL | 1.7 | 1.95 | V | HV POR turns off (VIP ↓), RL = open, VDD = 5.5V (change in ISS) | 10 | |
| HV POR trip voltage, turn-on (VIP ↑) | VPHH | 2.05 | 2.6 | V | HV POR turns on (VIP ↑), RL = open, VDD = 5.5V (change in ISS) | 10 | |
| Low supply voltage VDD (range) | VDD | 2 | 5.5 | V | All | 10 | |
| Quiescent current at VDD | IDD | 300 | 490 | 725 | μA | 10 | |
| Voltage across VDD, VSS | VDD -VSS | -0.3 | 5.5 | V | 5 | ||
| Current at input pins | -2 | 2 | mA | Note 1 | 5 | ||
| Analog inputs VIP and VIM | VIP, VIM | -0.3 | 70 | V | Note 1 | 5 | |
| Input difference voltage VDM | VDM | -1.2 | 1.2 | V | Note 1 | 5 | |
| Current at output and supply pins | -30 | 30 | mA | 5 | |||
| Storage temperature (absolute maximum) | -65 | 150 | °C | 5 | |||
| Maximum junction temperature | 155 | °C | Note 2 (not intended for continuous use) | 5 | |||
| ESD protection, HBM | 2 | kV | HBM, printed ≥ 2 kV | 5 | |||
| Specified temperature range TA (E-Temp) | TA | -40 | 125 | °C | E-Temp parts (Note 2) | 12 | |
| Operating temperature range | -40 | 150 | °C | Note 1 | 12 | ||
| Storage temperature range (Table 1-4) | -60 | 150 | °C | No power | 12 | ||
| Thermal resistance, 6L-SOT-23 junction to ambient | JA | 191 | °C/W | 6L-SOT-23 package | 12 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | gold | Package: CHY = Plastic Small Outline Transistor (SOT-23(2)), 6-Lead Nickel-Palladium-Gold Leadframe | 57 |
CAD (KiCad official)
- Symbol:
MCP6C02T-020E - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
mcp6c02t-020e-etched.step/mcp6c02t-020e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp6c02t-020e.step/mcp6c02t-020e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (60 pp, sha256
8f83a00c6bea0e6e, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP6C02T-020E
**Microchip Tech** · Current Sense Amplifiers · SOT-23-6
MCP6C02T-020E from Microchip Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | The analog output pin is a low-impedance voltage source, normally between VSS and VDD. |
| 2 | VSS | power_in | Negative power supply, connected to ground in a single positive supply configuration; it needs good bypass capacitors and must be tied to the exposed pad. |
| 3 | VIP | input | Noninverting high-impedance input treated as the common-mode voltage, normally VSS + 3V to VSS + 65V, and also the high-voltage supply pin that triggers the HV POR; it needs a bypass capacitor (e.g., 10 nF) and a limited edge rate so the ESD diodes do not clamp. |
| 4 | VIM | input | Inverting high-impedance CMOS input with low input bias current, designed to operate near the VIP voltage, with VDM = VIP - VIM as the input signal. |
| 5 | VREF | power_in | High-impedance CMOS analog output reference voltage set to a DC level that shifts VOUT, and whose dynamic response helps reject supply glitches. |
| 6 | VDD | power_in | Positive low-side power supply, normally VSS + 2.0V to VSS + 5.5V, which triggers the LV POR and needs good bypass capacitors. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOT-23-6 |
| Category | Amplifiers/Comparators |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Low supply voltage VDD, specified minimum (LV POR on) | VDDL | 2 | | | V | All; VDD ↑ (LV POR on) | 5 |
| Low supply voltage VDD, operating minimum | VDDL | 1.7 | | | V | | 5 |
| Supply voltage VDD, specified maximum | VDDH | | | 5.5 | V | | 5 |
| Supply voltage VDD, operating maximum | VDDH | | | 5.5 | V | | 5 |
| Common-mode input VIP, specified minimum (HV POR on) | VIPL | 3 | | | V | VIP ↑ (HV POR on) | 5 |
| Common-mode input VIP, operating minimum (HV POR on) | VIPL | 2.8 | | | V | VIP ↑ (HV POR on) | 5 |
| VIP falling POR threshold, specified minimum | VIPLD | 2.8 | | | V | VIP ↓ (HV POR on) | 5 |
| VIP falling POR threshold, operating minimum | VIPLD | 2.6 | | | V | VIP ↓ (HV POR on) | 5 |
| Common-mode input VIP, specified maximum | VIPH | | | 65 | V | | 5 |
| Common-mode input VIP, operating maximum | VIPH | | | 68 | V | | 5 |
| VREF, specified minimum | VRL | 0 | | | V | All | 6 |
| VREF, operating minimum | VRL | 0 | | | V | | 6 |
| VOUT minimum (specified, at RL = 1kΩ) | VOL | 0.06 | | | V | Note 5: VOL and VOH at RL = 1kΩ | 6 |
| Input offset voltage VOS (GDM = 20) | VOS | -16 | 1.9 | 16 | μV | GDM = 20; Input Offset (VIP = VIM); Note 2 | 7 |
| VOS linear drift TC1 (GDM = 20, E-Temp) | TC1 | -90 | 10 | 90 | nV/°C | GDM = 20; TA = -40°C to +125°C, for E-Temp parts (Note 2, Note 3) | 7 |
| Power supply rejection ratio (GDM = 20) | PSRR | 109 | 134 | | dB | GDM = 20; VDD = 2.0V to 5.5V | 7 |
| VIP input bias current | IBP | 120 | 170 | 215 | μA | VDD = 2.0V to 5.5V | 7 |
| VIP voltage range low (rising) | VIPL | | 2.4 | 3 | V | VIP ↑ | 8 |
| VIP voltage range low (falling POR threshold) | VIPLD | 2.15 | | 2.8 | V | VIP ↓ | 8 |
| VIP voltage range high | VIPH | 65 | | | V | | 8 |
| Common-mode rejection ratio (GDM = 20) | CMRR | 132 | 159 | | dB | GDM = 20; VDD = 2.0V to 5.5V, VIP = 3V to 65V | 8 |
| Reference voltage VREF lower limit | VRL | | | 0 | V | All; See Section 5.1.8, Setting the Voltage at VREF | 8 |
| Differential gain error gE (GDM = 20) | gE | -1.6 | 0.1 | 1.6 | % | VDD = 5.5V, VREF = 2.75V, GDMVDM = -2.65V to 2.65V | 8 |
| Minimum output voltage swing VOL (at RL = 1kΩ) | VOL | | 20 | 60 | mV | VDD = 5.5V, VREF = 0V, VDM = -0.5V/GDM, RL = 1kΩ | 9 |
| Maximum output voltage swing VDD, VOH (at RL = 1kΩ) | VDD, VOH | | 40 | 130 | mV | VDD = 5.5V, VREF = 4.25V, VDM = 1.75V/GDM, RL = 1kΩ | 9 |
| LV POR trip voltage, turn-off (VDD ↓) | VPLL | 1.05 | 1.35 | | V | LV POR turns off (VDD ↓), VL = 0V, VIP = 3V, VREF = 0V | 10 |
| LV POR trip voltage, turn-on (VDD ↑) | VPLH | | 1.45 | 1.7 | V | LV POR turns on (VDD ↑), VL = 0V, VIP = 3V, VREF = 0V | 10 |
| HV POR trip voltage, turn-off (VIP ↓) | VPHL | 1.7 | 1.95 | | V | HV POR turns off (VIP ↓), RL = open, VDD = 5.5V (change in ISS) | 10 |
| HV POR trip voltage, turn-on (VIP ↑) | VPHH | | 2.05 | 2.6 | V | HV POR turns on (VIP ↑), RL = open, VDD = 5.5V (change in ISS) | 10 |
| Low supply voltage VDD (range) | VDD | 2 | | 5.5 | V | All | 10 |
| Quiescent current at VDD | IDD | 300 | 490 | 725 | μA | | 10 |
| Voltage across VDD, VSS | VDD -VSS | -0.3 | | 5.5 | V | | 5 |
| Current at input pins | | -2 | | 2 | mA | Note 1 | 5 |
| Analog inputs VIP and VIM | VIP, VIM | -0.3 | | 70 | V | Note 1 | 5 |
| Input difference voltage VDM | VDM | -1.2 | | 1.2 | V | Note 1 | 5 |
| Current at output and supply pins | | -30 | | 30 | mA | | 5 |
| Storage temperature (absolute maximum) | | -65 | | 150 | °C | | 5 |
| Maximum junction temperature | | | | 155 | °C | Note 2 (not intended for continuous use) | 5 |
| ESD protection, HBM | | 2 | | | kV | HBM, printed ≥ 2 kV | 5 |
| Specified temperature range TA (E-Temp) | TA | -40 | | 125 | °C | E-Temp parts (Note 2) | 12 |
| Operating temperature range | | -40 | | 150 | °C | Note 1 | 12 |
| Storage temperature range (Table 1-4) | | -60 | | 150 | °C | No power | 12 |
| Thermal resistance, 6L-SOT-23 junction to ambient | JA | | 191 | | °C/W | 6L-SOT-23 package | 12 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | gold | Package: CHY = Plastic Small Outline Transistor (SOT-23(2)), 6-Lead Nickel-Palladium-Gold Leadframe | 57 |
## CAD (KiCad official)
- Symbol: `MCP6C02T-020E`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `mcp6c02t-020e-etched.step` / `mcp6c02t-020e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp6c02t-020e.step` / `mcp6c02t-020e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589795358386782208) (60 pp, sha256 `8f83a00c6bea0e6e`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp6c02t-020e-datasheet.pdf)