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MCP6487T-E

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Microchip Tech Operational Amplifier, SOIC-8-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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MCP6487T-E

Microchip Tech · Operational Amplifier · SOIC-8-150mil

MCP6487T-E from Microchip Tech, in a SOIC-8-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUTA output Analog output of op amp A, a low-impedance voltage source.
2 VINA- input Inverting input of op amp A, a high-impedance CMOS input with low bias current.
3 VINA+ input Noninverting input of op amp A, a high-impedance CMOS input with low bias current.
4 VSS power_in Negative power supply, connected to ground in single-supply use; VDD must be 1.8V to 5.5V higher than VSS.
5 VINB+ input Noninverting input of op amp B, a high-impedance CMOS input with low bias current.
6 VINB- input Inverting input of op amp B, a high-impedance CMOS input with low bias current.
7 VOUTB output Analog output of op amp B, a low-impedance voltage source.
8 VDD power_in Positive power supply, 1.8V to 5.5V above VSS, and it needs bypass capacitors.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8-150mil
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Absolute Maximum VDD, VSS 6 V 2
Current at Analog Input Pins VIN+, VIN- -5 5 mA ±5 mA 2
Analog Inputs Voltage VIN+, VIN- -0.5 0.5 V VSS, 0.5V to VDD + 0.5V (min relative to VSS, max relative to VDD) 2
Analog Outputs Voltage VOUT -0.3 0.3 V VSS - 0.3V to VDD + 0.3V (relative to VSS / VDD) 2
Storage Temperature -65 150 °C 2
Maximum Junction Temperature TJ 150 °C 2
Input Offset Voltage VOS -1.6 1.6 mV TA=+25°C, VDD=+1.8V to +5.5V, VCM=VDD/4 2
Power Supply Rejection Ratio PSRR 82 100 dB 2
Common Mode Input Voltage Range (25°C) VCMR -0.3 0.3 V VSS, 0.3 to VDD + 0.3 (relative to VSS / VDD) 2
Common Mode Input Voltage Range (Temp) VCMR -0.1 0.1 V VSS, 0.1 to VDD + 0.1; TA=-40°C to +125°C, Guaranteed by Characterization 2
Common Mode Rejection Ratio CMRR 66 110 dB VDD = 5.5V, VCM = -0.3V to 5.8V 2
DC Open-Loop Gain AOL 105 130 dB 0.2 < VOUT < (VDD -0.2V) 3
High-Level Output Voltage VOH -10 -3.5 mV VDD = 5.5V, RL = 10 k; printed VDD, 10 min, VDD, 3.5 typ (relative to VDD) 3
High-Level Output Voltage VOH -50 -30 mV VDD = 5.5V, RL = 1 k; printed VDD, 50 min, VDD, 30 typ (relative to VDD) 3
Low-Level Output Voltage VOL 3.5 10 mV VDD = 5.5V, RL = 10 k; printed VSS + 3.5 typ, VSS + 10 max (relative to VSS) 3
Low-Level Output Voltage VOL 30 50 mV VDD = 5.5V, RL = 1 k; printed VSS + 30 typ, VSS + 50 max (relative to VSS) 3
Supply Voltage VDD 1.8 5.5 V 3
Quiescent Current per Amplifier IQ 550 720 µA IO = 0 3
Operating Temperature Range TA -40 125 °C Note 1 4
Storage Temperature Range TA -65 150 °C 4
Thermal Resistance, 8L-SOIC θJA 150 °C/W 4
Input Offset Drift with Temperature ΔVOS/ΔTA 0.6 µV/°C TA= -40°C to +125°C; printed ±0.6 2
Input Bias Current IB 1 pA printed ±1 2
Input Bias Current IB 19 pA TA = +85°C 2
Input Bias Current IB 200 pA TA = +125°C 2
Input Offset Current IOS 1 pA printed ±1 2
Common Mode Rejection Ratio CMRR 125 dB VDD = 5.5V, VCM = -0.1V to 4.1V 2
Common Mode Rejection Ratio CMRR 75 dB VDD = 1.8V, VCM = -0.3V to 2.1V 2
Output Short-Circuit Current ISC 11 mA VDD = 1.8V; printed ±11 3
Output Short-Circuit Current ISC 50 mA VDD = 5.5V; printed ±50 3
Startup Time tstart 2.3 µs VDD = 0V to 5.5V 3
Gain Bandwidth Product GBWP 10 MHz 3
Phase Margin PM 60 ° G = +1 V/V 3
Slew Rate SR 20 V/µs VDD = 5.5V, VIN > 4V 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] A A2 25

CAD (KiCad official)

  • Symbol: MCP6487T-E
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8-150mil (KiCad packages3D, STEP)
  • 3D model files: mcp6487t-e-etched.step / mcp6487t-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp6487t-e.step / mcp6487t-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (46 pp, sha256 eebcf2effb2143f3, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF