component
MCP622-E
Public Made by Adomby adom
Microchip Tech Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownMCP622-E
Microchip Tech · Operational Amplifier · SOIC-8
MCP622-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Output of op amp A, a low-impedance voltage source. |
| 2 | VINA- | input | Inverting input of op amp A, a high-impedance CMOS input with low bias current. |
| 3 | VINA+ | input | Non-inverting input of op amp A, a high-impedance CMOS input with low bias current. |
| 4 | VSS | power_in | Negative power supply, normally connected to ground in single-supply use. |
| 5 | VINB+ | input | Non-inverting input of op amp B, a high-impedance CMOS input with low bias current. |
| 6 | VINB- | input | Inverting input of op amp B, a high-impedance CMOS input with low bias current. |
| 7 | VOUTB | output | Output of op amp B, a low-impedance voltage source. |
| 8 | VDD | power_in | Positive power supply, 2.5V to 5.5V above VSS, needs bypass capacitors. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Operational Amplifier/Comparator |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage | VOS | -200 | 200 | µV | After calibration (Note 1) | 3 | |
| Input Offset Voltage Trim Step Size | VOSTRM | 37 | 200 | µV | (Note 2) | 3 | |
| Power Supply Rejection Ratio | PSRR | 61 | 76 | dB | 3 | ||
| Input Bias Current across temperature | IB | 1700 | 5000 | pA | TA = +125°C | 3 | |
| Common Mode Rejection Ratio | CMRR | 65 | 81 | dB | VDD = 2.5V, VCM = -0.3 to 1.2V | 3 | |
| Common Mode Rejection Ratio | CMRR | 68 | 84 | dB | VDD = 5.5V, VCM = -0.3 to 4.2V | 3 | |
| DC Open-Loop Gain | AOL | 88 | 117 | dB | VDD = 2.5V, VOUT = 0.3V to 2.2V | 3 | |
| DC Open-Loop Gain | AOL | 94 | 126 | dB | VDD = 5.5V, VOUT = 0.3V to 5.2V | 3 | |
| Output Short Circuit Current (magnitude) | ISC | 40 | 85 | 130 | mA | VDD = 2.5V (Note 4) | 4 |
| Output Short Circuit Current (magnitude) | ISC | 35 | 70 | 110 | mA | VDD = 5.5V (Note 4) | 4 |
| Supply Voltage | VDD | 2.5 | 5.5 | V | 4 | ||
| Quiescent Current per Amplifier | IQ | 1.2 | 2.5 | 3.6 | mA | IO = 0 | 4 |
| POR Input Threshold, Low | VPRL | 1.15 | 1.4 | V | 4 | ||
| POR Input Threshold, High | VPRH | 1.4 | 1.65 | V | 4 | ||
| VDD High to Amplifier On Time (including calibration) | tPON | 100 | 200 | 300 | ms | G = +1 V/V, VL = VSS, VDD = 0V to 2.5V step to VOUT = 0.9 (2.5V) | 5 |
| Specified Temperature Range | TA | -40 | 125 | °C | 6 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | (Note 1) | 6 | |
| Current at Input Pins | -2 | 2 | mA | 3 | |||
| Current at Output and Supply Pins | -150 | 150 | mA | 3 | |||
| Storage Temperature | -65 | 150 | °C | 3 | |||
| Max. Junction Temperature | TJ | 150 | °C | 3 | |||
| Thermal Resistance, 8L-SOIC | θJA | 149.5 | °C/W | 6 | |||
| Input Offset Voltage Drift | ΔVOS/ΔTA | 2 | µV/°C | TA = -40°C to +125°C | 3 | ||
| Input Bias Current | IB | 5 | pA | 3 | |||
| Input Bias Current across temperature | IB | 100 | pA | TA = +85°C | 3 | ||
| Gain Bandwidth Product | GBWP | 20 | MHz | 4 | |||
| Phase Margin | PM | 60 | ° | G = +1 | 4 | ||
| Slew Rate | SR | 10 | V/µs | G = +1 | 4 | ||
| Input Noise Voltage Density | eni | 13 | nV/√Hz | f = 1 MHz | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | OT = Plastic Small Outline (SOT-23), 5-lead SN = Plastic Small Outline, (3.90 mm), 8-lead | 60 |
CAD (KiCad official)
- Symbol:
MCP622-E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp622-e-etched.step/mcp622-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp622-e.step/mcp622-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (62 pp, sha256
fa78c556b80f3b03, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).