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MCP62

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Mysentech Float Level Senors, QSOP-24. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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MCP62

Mysentech · Float Level Senors · QSOP-24

MCP62 from Mysentech, in a QSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 C1A passive Channel 1 capacitor input (analog). Positive terminal of the sensing capacitor for channel 1; connects to the external inductor L / sensing capacitor Cp network.
2 C1B passive Channel 1 capacitor ground (analog). Negative/return terminal of the channel-1 sensing capacitor; internally tied to GNDA through the chip in dual-electrode mode.
3 VC passive Reference voltage pin for the capacitive AFE. Typically bypassed with an external decoupling capacitor.
4 VT passive Temperature-sensing voltage pin (analog). Used together with the on-chip temperature sensor for temperature compensation.
5 RUP passive External resistor pin (standard I/O, TC level). Sets the AFE drive/pull-up current via an external resistor to VDD.
6 GND power_in Digital ground return, 0 V reference for the digital core and I/O.
7 PA15 bidirectional General-purpose I/O PA15 (standard TC-level I/O, input tolerant to VDD). Alt functions: SPI1_NSS, TIM1_CH3N, SPI1_MOSI, TIM3_CH3; ADC1_VIN[6] additional analog input.
8 PA2 bidirectional General-purpose I/O PA2 (standard TC I/O). Alt functions: TIM1_CH2N, SPI1_MISO, TIM3_CH2; ADC1_VIN[5] additional analog input.
9 PA12 bidirectional General-purpose I/O PA12 (standard TC I/O). Alt function: USART1_TX; ADC1_VIN[3] additional analog input.
10 PA3 bidirectional General-purpose I/O PA3 (standard TC I/O). Alt functions: USART1_RX, USART2_SCK, SPI1_NSS; ADC1_VIN[2] additional analog input.
11 PA14(NRST) bidirectional General-purpose I/O PA14 (standard TC I/O). Alt functions: SWCLK (serial-wire debug clock), USART1_TX, SPI1_SCK. When RCC_SYSCFG SFT_NRST_RMP=1 the pin is remapped as external reset (NRST) and reset low must be held >=4 us.
12 PB0(OSCIN) bidirectional General-purpose I/O PB0 (standard TC I/O). Alt function: USART2_SCK; ADC1_VIN[1] additional analog input. Can be configured as the external HSE clock input (OSCIN) up to 48 MHz.
13 PA1 bidirectional General-purpose I/O PA1 (standard TC I/O). Alt functions: USART1_SCK, USART2_TX, I2C1_SDA, SPI1_MOSI.
14 VDD power_in Digital power supply input, 2.5 V to 5.5 V. Feeds the MCU core and digital I/O; decouple locally with a bypass capacitor.
15 PA13 bidirectional General-purpose I/O PA13 (standard TC I/O). Alt functions: SWDIO (serial-wire debug data), USART1_RX, USART2_RX, I2C1_SCL, SPI1_MISO.
16 PA10 bidirectional General-purpose I/O PA10 (standard TC I/O). Alt functions: SPI1_MISO, TIM1_CH3, TIM1_CH2, MCO (master clock output), USART1_TX.
17 PA0 bidirectional General-purpose I/O PA0 (standard TC I/O). Alt functions: SPI1_NSS, USART1_RX, TIM1_CH3N, I2C1_SCL, TIM3_CH3.
18 PA4 bidirectional General-purpose I/O PA4 (standard TC I/O). Alt functions: TIM1_BKIN, I2C1_SDA, TIM3_CH4.
19 PA5 bidirectional General-purpose I/O PA5 (standard TC I/O). Alt functions: SPI1_SCK, TIM1_CH1N, I2C1_SCL.
20 GND power_in Digital ground return (second GND pin), 0 V reference for the digital core and I/O.
21 VDDA power_in Analog power supply input for the capacitive AFE and ADC. Typically tied to VDD through a low-impedance filter; decouple with a local bypass capacitor.
22 GNDA power_in Analog ground return, 0 V reference for VDDA / AFE / ADC. Should be joined to digital GND at a single star point.
23 C0A passive Channel 0 capacitor input (analog). Positive terminal of the sensing capacitor for channel 0; connects to the external inductor L / sensing capacitor Cp network.
24 C0B passive Channel 0 capacitor ground (analog). Negative/return terminal of the channel-0 sensing capacitor; internally tied to GNDA through the chip in dual-electrode mode.

Key specifications

Parameter Value
Manufacturer Mysentech
Package QSOP-24
Category Sensor
Pins 24

Ordering variants

Same part, different packaging or reel option.

  • MCP62
  • MCP62G

CAD (KiCad official)

  • Symbol: MCP62
  • Footprint: Package_SO:QSOP-24_3.9x8.7mm_P0.635mm
  • 3D model: QSOP-24 (KiCad packages3D, STEP)
  • 3D model files: mcp62-etched.step / mcp62-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp62.step / mcp62.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Mysentech datasheet (44 pp, sha256 6645f2df8e6822c7, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF