component

MCP6022T-I

Public Made by Adom

by adom

Microchip Operational Amplifier, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs mcp6022t-i: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
mcp6022t-i-etched.fit.json mcp6022t-i: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
mcp6022t-i-etched.glb mcp6022t-i: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
mcp6022t-i-etched.step mcp6022t-i: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
mcp6022t-i.glb Publish 0.1.0 · Ray 1mo ago
mcp6022t-i.kicad_mod Publish 0.1.0 · Ray 1mo ago
mcp6022t-i.kicad_sym Publish 0.1.0 · Ray 1mo ago
mcp6022t-i.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 8 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
mcp6022t-i.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json mcp6022t-i: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 21h ago
README.md mcp6022t-i: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 19d ago

MCP6022T-I

Microchip · Operational Amplifier · SOIC-8

MCP6022T-I from Microchip, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUTA output Analog output of op amp A. Low-impedance rail-to-rail output; swings to within ~20 mV of either supply rail with a 10 kΩ load. Short-circuit current is ~±30 mA at VDD=2.5 V and ~±22 mA at VDD=5.5 V (continuous short-circuit rated).
2 VINA- input Inverting analog input of op amp A. High-impedance CMOS input with ~1 pA typical bias current; must remain within VSS-1.0 V to VDD+1.0 V and current into the pin limited to ±2 mA per absolute maximum ratings.
3 VINA+ input Non-inverting analog input of op amp A. High-impedance CMOS input, common-mode range VSS-0.3 V to VDD+0.3 V (rail-to-rail input). CMRR typically 90 dB at VDD=5 V.
4 VSS power_in Negative power supply / ground reference for both amplifiers. Typically tied to GND in single-supply designs; VDD-VSS must not exceed 7.0 V (absolute max).
5 VINB+ input Non-inverting analog input of op amp B. High-impedance CMOS input with rail-to-rail common-mode range (VSS-0.3 V to VDD+0.3 V).
6 VINB- input Inverting analog input of op amp B. High-impedance CMOS input; obey ±2 mA input current and VSS-1.0 V to VDD+1.0 V voltage limits.
7 VOUTB output Analog output of op amp B. Low-impedance rail-to-rail output with the same drive characteristics as VOUTA; short-circuit protected (continuous).
8 VDD power_in Positive power supply, 2.5 V to 5.5 V (6.0 V absolute max above VSS). Bypass with a local 0.1 µF ceramic (plus optional 1 µF bulk) close to the pin. Quiescent current is ~1.0 mA typical per amplifier (so ~2 mA total for the dual).

Key specifications

Parameter Value
Manufacturer Microchip
Package SOIC-8
Category Op-amp/Cmp
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • MCP6022T-II/SN
  • MCP6022T-I/SN
  • MCP6022T-II/ST
  • MCP6022T-I/ST
  • MCP6022T-II/P

CAD (KiCad official)

  • Symbol: MCP6022T-I
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: mcp6022t-i-etched.step / mcp6022t-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp6022t-i.step / mcp6022t-i.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
mcp6022t-i.step 122 KB You want the bare part, or you mark your own boards.
mcp6022t-i-etched.step 2.0 MB You want the part with MCP6022T-I already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 491 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip datasheet (42 pp, sha256 968bbb977d7ab454, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF