component
MCP6021-I
Public Made by Adomby adom
Microchip Tech Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MCP6021-I
Microchip Tech · Operational Amplifier · SOIC-8
MCP6021-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No internal connection. |
| 2 | VIN- | power_in | Inverting input of the op amp, a high-impedance CMOS input with low bias current. |
| 3 | VIN+ | power_in | Non-inverting input of the op amp, a high-impedance CMOS input with low bias current. |
| 4 | VSS | power_in | Negative power supply pin, connected to ground in single-supply use; VDD must be 2.5V to 5.5V above it. |
| 5 | VREF | power_in | Mid-supply reference voltage from an unbuffered, internal resistor voltage divider. |
| 6 | VOUT | output | Analog op amp output, a low-impedance voltage source. |
| 7 | VDD | power_in | Positive power supply pin, 2.5V to 5.5V above VSS, and needs a bypass capacitor. |
| 8 | NC | unconnected | No internal connection. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Amplifiers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage (Industrial) | VOS | -500 | 500 | µV | VCM = 0V | 3 | |
| Power Supply Rejection Ratio | PSRR | 74 | 90 | dB | VCM = 0V | 3 | |
| Input Bias Current (Industrial) | IB | 30 | 150 | pA | TA = +85°C | 3 | |
| Common-Mode Rejection Ratio | CMRR | 74 | 90 | dB | VDD = 5V, VCM = -0.3V to 5.3V | 3 | |
| Common-Mode Rejection Ratio | CMRR | 70 | 85 | dB | VDD = 5V, VCM = 3.0V to 5.3V | 3 | |
| VREF Accuracy (VREF, VDD/2) | VREF_ACC | -50 | 50 | mV | 3 | ||
| DC Open-Loop Gain (Large Signal) | AOL | 90 | 110 | dB | VCM = 0V, VOUT = VSS + 0.3V to VDD, 0.3V | 3 | |
| Supply Voltage | VDD | 2.5 | 5.5 | V | 3 | ||
| Quiescent Current per Amplifier | IQ | 0.5 | 1 | 1.35 | mA | IO = 0 | 3 |
| Industrial Temperature Range | TA | -40 | 85 | °C | 5 | ||
| Storage Temperature Range | TA | -65 | 150 | °C | 5 | ||
| Supply Voltage VDD, VSS | VDD-VSS | 7 | V | 3 | |||
| Current Analog Input Pins (VIN+, VIN-) | -2 | 2 | mA | 3 | |||
| Current at Output and Supply Pins | -30 | 30 | mA | 3 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 3 | |||
| ESD Protection on All Pins (HBM) | 2 | kV | HBM | 3 | |||
| ESD Protection on All Pins (MM) | 200 | V | MM | 3 | |||
| Thermal Resistance, 8L-SOIC | θJA | 163 | °C/W | 5 | |||
| Input Offset Voltage Temperature Drift | ΔVOS/ΔTA | 3.5 | µV/°C | TA = -40°C to +125°C; printed as ±3.5 | 3 | ||
| VREF Temperature Drift | ΔVREF/ΔTA | 100 | µV/°C | TA = -40°C to +125°C; printed as ±100 | 3 | ||
| Input Bias Current | IB | 1 | pA | 3 | |||
| Input Offset Current | IOS | 1 | pA | printed as ±1 | 3 | ||
| Output Short Circuit Current | ISC | 30 | mA | VDD = 2.5V; printed as ±30 | 3 | ||
| Output Short Circuit Current | ISC | 22 | mA | VDD = 5.5V; printed as ±22 | 3 | ||
| Gain Bandwidth Product | GBWP | 10 | MHz | 4 | |||
| Phase Margin | PM | 65 | ° | G = +1 V/V | 4 | ||
| Slew Rate | SR | 7 | V/µs | 4 | |||
| Settling Time, 0.2% | tSETTLE | 250 | ns | G = +1 V/V, VOUT = 100 mVp-p | 4 | ||
| Input Noise Voltage Density | eni | 8.7 | nV/√Hz | f = 10 kHz | 4 | ||
| Input Noise Voltage | Eni | 2.9 | µVp-p | f = 0.1 Hz to 10 Hz | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | P = Plastic DIP (300 mil Body), 8-Lead, 14-Lead SN = Plastic SOIC (150 mil Body), 8-Lead | 51 |
CAD (KiCad official)
- Symbol:
MCP6021-I - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp6021-i-etched.step/mcp6021-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp6021-i.step/mcp6021-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (54 pp, sha256
899b5ff27b9b1a7b, retrieved 2026-10-24, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP6021-I
**Microchip Tech** · Operational Amplifier · SOIC-8
MCP6021-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No internal connection. |
| 2 | VIN- | power_in | Inverting input of the op amp, a high-impedance CMOS input with low bias current. |
| 3 | VIN+ | power_in | Non-inverting input of the op amp, a high-impedance CMOS input with low bias current. |
| 4 | VSS | power_in | Negative power supply pin, connected to ground in single-supply use; VDD must be 2.5V to 5.5V above it. |
| 5 | VREF | power_in | Mid-supply reference voltage from an unbuffered, internal resistor voltage divider. |
| 6 | VOUT | output | Analog op amp output, a low-impedance voltage source. |
| 7 | VDD | power_in | Positive power supply pin, 2.5V to 5.5V above VSS, and needs a bypass capacitor. |
| 8 | NC | unconnected | No internal connection. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Amplifiers |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage (Industrial) | VOS | -500 | | 500 | µV | VCM = 0V | 3 |
| Power Supply Rejection Ratio | PSRR | 74 | 90 | | dB | VCM = 0V | 3 |
| Input Bias Current (Industrial) | IB | | 30 | 150 | pA | TA = +85°C | 3 |
| Common-Mode Rejection Ratio | CMRR | 74 | 90 | | dB | VDD = 5V, VCM = -0.3V to 5.3V | 3 |
| Common-Mode Rejection Ratio | CMRR | 70 | 85 | | dB | VDD = 5V, VCM = 3.0V to 5.3V | 3 |
| VREF Accuracy (VREF, VDD/2) | VREF_ACC | -50 | | 50 | mV | | 3 |
| DC Open-Loop Gain (Large Signal) | AOL | 90 | 110 | | dB | VCM = 0V, VOUT = VSS + 0.3V to VDD, 0.3V | 3 |
| Supply Voltage | VDD | 2.5 | | 5.5 | V | | 3 |
| Quiescent Current per Amplifier | IQ | 0.5 | 1 | 1.35 | mA | IO = 0 | 3 |
| Industrial Temperature Range | TA | -40 | | 85 | °C | | 5 |
| Storage Temperature Range | TA | -65 | | 150 | °C | | 5 |
| Supply Voltage VDD, VSS | VDD-VSS | | | 7 | V | | 3 |
| Current Analog Input Pins (VIN+, VIN-) | | -2 | | 2 | mA | | 3 |
| Current at Output and Supply Pins | | -30 | | 30 | mA | | 3 |
| Maximum Junction Temperature | TJ | | | 150 | °C | | 3 |
| ESD Protection on All Pins (HBM) | | 2 | | | kV | HBM | 3 |
| ESD Protection on All Pins (MM) | | 200 | | | V | MM | 3 |
| Thermal Resistance, 8L-SOIC | θJA | | 163 | | °C/W | | 5 |
| Input Offset Voltage Temperature Drift | ΔVOS/ΔTA | | 3.5 | | µV/°C | TA = -40°C to +125°C; printed as ±3.5 | 3 |
| VREF Temperature Drift | ΔVREF/ΔTA | | 100 | | µV/°C | TA = -40°C to +125°C; printed as ±100 | 3 |
| Input Bias Current | IB | | 1 | | pA | | 3 |
| Input Offset Current | IOS | | 1 | | pA | printed as ±1 | 3 |
| Output Short Circuit Current | ISC | | 30 | | mA | VDD = 2.5V; printed as ±30 | 3 |
| Output Short Circuit Current | ISC | | 22 | | mA | VDD = 5.5V; printed as ±22 | 3 |
| Gain Bandwidth Product | GBWP | | 10 | | MHz | | 4 |
| Phase Margin | PM | | 65 | | ° | G = +1 V/V | 4 |
| Slew Rate | SR | | 7 | | V/µs | | 4 |
| Settling Time, 0.2% | tSETTLE | | 250 | | ns | G = +1 V/V, VOUT = 100 mVp-p | 4 |
| Input Noise Voltage Density | eni | | 8.7 | | nV/√Hz | f = 10 kHz | 4 |
| Input Noise Voltage | Eni | | 2.9 | | µVp-p | f = 0.1 Hz to 10 Hz | 4 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | P = Plastic DIP (300 mil Body), 8-Lead, 14-Lead SN = Plastic SOIC (150 mil Body), 8-Lead | 51 |
## CAD (KiCad official)
- Symbol: `MCP6021-I`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `mcp6021-i-etched.step` / `mcp6021-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp6021-i.step` / `mcp6021-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/mcp6021-i-datasheet.pdf) (54 pp, sha256 `899b5ff27b9b1a7b`, retrieved 2026-10-24, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp6021-i-datasheet.pdf)