component
MCP4912-E
Public Made by Adomby adom
Microchip Tech Digital To Analog Converters (DACs), SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MCP4912-E
Microchip Tech · Digital To Analog Converters (DACs) · SOIC-14
MCP4912-E from Microchip Tech, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply voltage input, 2.7V to 5.5V relative to VSS; bypass with about 0.1 µF ceramic plus 10 µF tantalum. |
| 2 | NC | unconnected | No connection. |
| 3 | CS | input | Chip Select input; active low signal enables serial clock and data functions. |
| 4 | SCK | input | SPI compatible serial clock input. |
| 5 | SDI | input | SPI compatible serial data input. |
| 6 | NC | unconnected | No connection. |
| 7 | NC | unconnected | No connection. |
| 8 | LDAC | input | Synchronization input that transfers input registers to the DAC output registers when low, updating VOUTA and VOUTB together; can be tied to VSS. |
| 9 | SHDN | input | Hardware shutdown input; when low both DAC channels are shut down and the output is not available. |
| 10 | VOUTB | output | DAC B output from its own output amplifier, driving a range of VSS to VDD. |
| 11 | VREFB | input | DAC B reference voltage input, range VSS to VDD; can be tied to VDD. |
| 12 | VSS | power_in | Ground reference point for all circuitry on the device and analog ground current return path. |
| 13 | VREFA | input | DAC A reference voltage input, range VSS to VDD; can be tied to VDD. |
| 14 | VOUTA | output | DAC A output from its own output amplifier, driving a range of VSS to VDD. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-14 |
| Category | ADC/DAC/Data Conversion |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Voltage | VDD | 2.7 | 5.5 | V | 3 | ||
| Operating Current | IDD | 350 | 700 | µA | VDD = 5V; VREF unbuffered, digital inputs grounded, outputs unloaded, Code = 000h | 3 | |
| Operating Current | IDD | 250 | 500 | µA | VDD = 3V; VREF unbuffered, digital inputs grounded, outputs unloaded, Code = 000h | 3 | |
| Hardware Shutdown Current | ISHDN | 0.3 | 2 | µA | Power-on Reset circuit is turned off | 3 | |
| Software Shutdown Current | ISHDN_SW | 3.3 | 6 | µA | Power-on Reset circuit stays on | 3 | |
| Power-on-Reset Threshold | VPOR | 2 | V | 3 | |||
| Resolution (MCP4912) | n | 10 | Bits | 3 | |||
| INL Error (MCP4912) | INL | -3.5 | 0.5 | 3.5 | LSb | typ printed as ±0.5 | 3 |
| DNL (MCP4912) | DNL | -0.5 | 0.1 | 0.5 | LSb | Note 1; typ printed as ±0.1 | 3 |
| Offset Error | VOS | 0.02 | 1 | % of FSR | Code = 0x000h; typ printed as ±0.02 | 3 | |
| Gain Error | gE | -0.1 | 1 | % of FSR | Code = 0xFFFh, not including offset error | 4 | |
| Input Range, Buffered Mode | VREF | 0.04 | V | VDD, 0.040 max; Note 2 | 4 | ||
| Short Circuit Current | ISC | 15 | 24 | mA | 4 | ||
| Schmitt Trigger High-Level Input Voltage | VIH | 0.7 | V | min is 0.7 VDD; all digital input pins | 7 | ||
| Schmitt Trigger Low-Level Input Voltage | VIL | 0.2 | V | max is 0.2 VDD; all digital input pins | 7 | ||
| Input Leakage Current | ILEAKAGE | -1 | 1 | µA | SHDN = LDAC = CS = SDI = SCK + VREF = VDD or VSS | 7 | |
| Clock Frequency | FCLK | 20 | MHz | TA = +25°C (Note 1) | 7 | ||
| Clock High Time | tHI | 15 | ns | Note 1 | 7 | ||
| Clock Low Time | tLO | 15 | ns | Note 1 | 7 | ||
| CS Fall to First Rising CLK Edge | tCSSR | 40 | ns | Applies only when CS falls with CLK high. (Note 1) | 7 | ||
| Data Input Setup Time | tSU | 15 | ns | Note 1 | 7 | ||
| Data Input Hold Time | tHD | 10 | ns | Note 1 | 7 | ||
| SCK Rise to CS Rise Hold Time | tCHS | 15 | ns | Note 1 | 7 | ||
| CS High Time | tCSH | 15 | ns | Note 1 | 7 | ||
| LDAC Pulse Width | tLD | 100 | ns | Note 1 | 7 | ||
| LDAC Setup Time | tLS | 40 | ns | Note 1 | 7 | ||
| SCK Idle Time before CS Fall | tIDLE | 40 | ns | Note 1 | 7 | ||
| INL Error (MCP4912), extended temperature | INL | -1 | 1 | LSb | Extended temperature table, printed ±1; typ at +125°C | 5 | |
| DNL (MCP4912), extended temperature | DNL | -0.2 | 0.2 | LSb | Extended temperature table, printed ±0.2; Note 1 | 5 | |
| Operating Current, extended temperature | IDD | 400 | µA | Typical at +125°C; VREF unbuffered, digital inputs grounded, outputs unloaded, Code=000h | 5 | ||
| Hardware Shutdown Current, extended temperature | ISHDN | 1.5 | µA | POR circuit is turned-off | 5 | ||
| Software Shutdown Current, extended temperature | ISHDN_SW | 5 | µA | POR circuit stays turned-on | 5 | ||
| Offset Error Temperature Coefficient | VOS/°C | 0.16 | ppm/°C | -45°C to 25°C | 4 | ||
| Offset Error Temperature Coefficient | VOS/°C | -0.44 | ppm/°C | +25°C to 85°C | 4 | ||
| Gain Error Temperature Coefficient | G/°C | -3 | ppm/°C | 4 | |||
| Offset Error Temperature Coefficient, extended | VOS/°C | -5 | ppm/°C | +25°C to +125°C | 5 | ||
| Input Impedance | RVREF | 165 | kΩ | Unbuffered Mode | 4 | ||
| Input Capacitance, Unbuffered Mode | CVREF | 7 | pF | 4 | |||
| Slew Rate | SR | 0.55 | V/µs | 4 | |||
| Settling Time | tsettling | 4.5 | µs | Within 1/2 LSb of final value from 1/4 to 3/4 full-scale range | 4 | ||
| Supply Voltage | VDD | 6.5 | V | 3 | |||
| Current at Input Pins | -2 | 2 | mA | 3 | |||
| Current at Supply Pins | -50 | 50 | mA | 3 | |||
| Current at Output Pins | -25 | 25 | mA | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Ambient temp. with power applied | -55 | 125 | °C | 3 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 3 | |||
| ESD protection on all pins (HBM) | 4 | kV | HBM | 3 | |||
| ESD protection on all pins (MM) | 400 | V | MM | 3 | |||
| Specified Temperature Range | TA | -40 | 125 | °C | 8 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | Note 1 | 8 | |
| Thermal Resistance, 14L-SOIC | θJA | 120 | °C/W | 8 |
CAD (KiCad official)
- Symbol:
MCP4912-E - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mcp4912-e-etched.step/mcp4912-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4912-e.step/mcp4912-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (48 pp, sha256
8c507a2bce321888, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP4912-E
**Microchip Tech** · Digital To Analog Converters (DACs) · SOIC-14
MCP4912-E from Microchip Tech, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply voltage input, 2.7V to 5.5V relative to VSS; bypass with about 0.1 µF ceramic plus 10 µF tantalum. |
| 2 | NC | unconnected | No connection. |
| 3 | CS | input | Chip Select input; active low signal enables serial clock and data functions. |
| 4 | SCK | input | SPI compatible serial clock input. |
| 5 | SDI | input | SPI compatible serial data input. |
| 6 | NC | unconnected | No connection. |
| 7 | NC | unconnected | No connection. |
| 8 | LDAC | input | Synchronization input that transfers input registers to the DAC output registers when low, updating VOUTA and VOUTB together; can be tied to VSS. |
| 9 | SHDN | input | Hardware shutdown input; when low both DAC channels are shut down and the output is not available. |
| 10 | VOUTB | output | DAC B output from its own output amplifier, driving a range of VSS to VDD. |
| 11 | VREFB | input | DAC B reference voltage input, range VSS to VDD; can be tied to VDD. |
| 12 | VSS | power_in | Ground reference point for all circuitry on the device and analog ground current return path. |
| 13 | VREFA | input | DAC A reference voltage input, range VSS to VDD; can be tied to VDD. |
| 14 | VOUTA | output | DAC A output from its own output amplifier, driving a range of VSS to VDD. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-14 |
| Category | ADC/DAC/Data Conversion |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Voltage | VDD | 2.7 | | 5.5 | V | | 3 |
| Operating Current | IDD | | 350 | 700 | µA | VDD = 5V; VREF unbuffered, digital inputs grounded, outputs unloaded, Code = 000h | 3 |
| Operating Current | IDD | | 250 | 500 | µA | VDD = 3V; VREF unbuffered, digital inputs grounded, outputs unloaded, Code = 000h | 3 |
| Hardware Shutdown Current | ISHDN | | 0.3 | 2 | µA | Power-on Reset circuit is turned off | 3 |
| Software Shutdown Current | ISHDN_SW | | 3.3 | 6 | µA | Power-on Reset circuit stays on | 3 |
| Power-on-Reset Threshold | VPOR | | 2 | | V | | 3 |
| Resolution (MCP4912) | n | 10 | | | Bits | | 3 |
| INL Error (MCP4912) | INL | -3.5 | 0.5 | 3.5 | LSb | typ printed as ±0.5 | 3 |
| DNL (MCP4912) | DNL | -0.5 | 0.1 | 0.5 | LSb | Note 1; typ printed as ±0.1 | 3 |
| Offset Error | VOS | | 0.02 | 1 | % of FSR | Code = 0x000h; typ printed as ±0.02 | 3 |
| Gain Error | gE | | -0.1 | 1 | % of FSR | Code = 0xFFFh, not including offset error | 4 |
| Input Range, Buffered Mode | VREF | 0.04 | | | V | VDD, 0.040 max; Note 2 | 4 |
| Short Circuit Current | ISC | | 15 | 24 | mA | | 4 |
| Schmitt Trigger High-Level Input Voltage | VIH | 0.7 | | | V | min is 0.7 VDD; all digital input pins | 7 |
| Schmitt Trigger Low-Level Input Voltage | VIL | | | 0.2 | V | max is 0.2 VDD; all digital input pins | 7 |
| Input Leakage Current | ILEAKAGE | -1 | | 1 | µA | SHDN = LDAC = CS = SDI = SCK + VREF = VDD or VSS | 7 |
| Clock Frequency | FCLK | | | 20 | MHz | TA = +25°C (Note 1) | 7 |
| Clock High Time | tHI | 15 | | | ns | Note 1 | 7 |
| Clock Low Time | tLO | 15 | | | ns | Note 1 | 7 |
| CS Fall to First Rising CLK Edge | tCSSR | 40 | | | ns | Applies only when CS falls with CLK high. (Note 1) | 7 |
| Data Input Setup Time | tSU | 15 | | | ns | Note 1 | 7 |
| Data Input Hold Time | tHD | 10 | | | ns | Note 1 | 7 |
| SCK Rise to CS Rise Hold Time | tCHS | 15 | | | ns | Note 1 | 7 |
| CS High Time | tCSH | 15 | | | ns | Note 1 | 7 |
| LDAC Pulse Width | tLD | 100 | | | ns | Note 1 | 7 |
| LDAC Setup Time | tLS | 40 | | | ns | Note 1 | 7 |
| SCK Idle Time before CS Fall | tIDLE | 40 | | | ns | Note 1 | 7 |
| INL Error (MCP4912), extended temperature | INL | -1 | | 1 | LSb | Extended temperature table, printed ±1; typ at +125°C | 5 |
| DNL (MCP4912), extended temperature | DNL | -0.2 | | 0.2 | LSb | Extended temperature table, printed ±0.2; Note 1 | 5 |
| Operating Current, extended temperature | IDD | | 400 | | µA | Typical at +125°C; VREF unbuffered, digital inputs grounded, outputs unloaded, Code=000h | 5 |
| Hardware Shutdown Current, extended temperature | ISHDN | | 1.5 | | µA | POR circuit is turned-off | 5 |
| Software Shutdown Current, extended temperature | ISHDN_SW | | 5 | | µA | POR circuit stays turned-on | 5 |
| Offset Error Temperature Coefficient | VOS/°C | | 0.16 | | ppm/°C | -45°C to 25°C | 4 |
| Offset Error Temperature Coefficient | VOS/°C | | -0.44 | | ppm/°C | +25°C to 85°C | 4 |
| Gain Error Temperature Coefficient | G/°C | | -3 | | ppm/°C | | 4 |
| Offset Error Temperature Coefficient, extended | VOS/°C | | -5 | | ppm/°C | +25°C to +125°C | 5 |
| Input Impedance | RVREF | | 165 | | kΩ | Unbuffered Mode | 4 |
| Input Capacitance, Unbuffered Mode | CVREF | | 7 | | pF | | 4 |
| Slew Rate | SR | | 0.55 | | V/µs | | 4 |
| Settling Time | tsettling | | 4.5 | | µs | Within 1/2 LSb of final value from 1/4 to 3/4 full-scale range | 4 |
| Supply Voltage | VDD | | | 6.5 | V | | 3 |
| Current at Input Pins | | -2 | | 2 | mA | | 3 |
| Current at Supply Pins | | -50 | | 50 | mA | | 3 |
| Current at Output Pins | | -25 | | 25 | mA | | 3 |
| Storage temperature | | -65 | | 150 | °C | | 3 |
| Ambient temp. with power applied | | -55 | | 125 | °C | | 3 |
| Maximum Junction Temperature | TJ | | | 150 | °C | | 3 |
| ESD protection on all pins (HBM) | | | | 4 | kV | HBM | 3 |
| ESD protection on all pins (MM) | | | | 400 | V | MM | 3 |
| Specified Temperature Range | TA | -40 | | 125 | °C | | 8 |
| Operating Temperature Range | TA | -40 | | 125 | °C | Note 1 | 8 |
| Thermal Resistance, 14L-SOIC | θJA | | 120 | | °C/W | | 8 |
## CAD (KiCad official)
- Symbol: `MCP4912-E`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `mcp4912-e-etched.step` / `mcp4912-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp4912-e.step` / `mcp4912-e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/mcp4912-e-datasheet.pdf) (48 pp, sha256 `8c507a2bce321888`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp4912-e-datasheet.pdf)