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MCP4902-E

Microchip Tech · Digital To Analog Converters (DACs) · TSSOP-14

MCP4902-E from Microchip Tech, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Positive supply voltage input, which must range from 2.7V to 5.5V relative to VSS and should be bypassed with about 0.1 µF ceramic plus 10 µF tantalum capacitors.
2 NC unconnected No connection.
3 CS input Active-low Chip Select input that enables the serial clock and data functions.
4 SCK input SPI-compatible serial clock input.
5 SDI input SPI-compatible serial data input.
6 NC unconnected No connection.
7 NC unconnected No connection.
8 LDAC input Synchronization input that transfers the input registers to the DAC output registers; when low, VOUTA and VOUTB update simultaneously, and it can be tied to VSS.
9 SHDN input Hardware shutdown input; when low, both DAC channels are shut down and the DAC output is not available.
10 VOUTB output DAC B analog output from its own output amplifier, which can drive the pin from VSS to VDD.
11 VREFB input Voltage reference input for DAC channel B, which accepts a signal from VSS to VDD and can be tied to VDD.
12 VSS power_in Analog ground and ground reference point for all device circuitry, which must be connected to a low-impedance ground plane.
13 VREFA input Voltage reference input for DAC channel A, which accepts a signal from VSS to VDD and can be tied to VDD.
14 VOUTA output DAC A analog output from its own output amplifier, which can drive the pin from VSS to VDD.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TSSOP-14
Category ADC/DAC/Data Conversion
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Voltage VDD 2.7 5.5 V 5
Resolution (MCP4902) n 8 Bits 5
INL Error (MCP4902) INL -0.25 0.25 LSb 5
DNL (MCP4902) DNL -0.2 0.2 LSb 5
Offset Error VOS -0.02 0.02 % of FSR Code 0x000h 5
Input Range - Unbuffered Mode (lower limit) VREF 0 V 5
Clock Frequency FCLK 20 MHz TA = +25°C 7
Clock High Time tHI 15 ns 7
Clock Low Time tLO 15 ns 7
CS Fall to First Rising CLK Edge tCSSR 40 ns Applies only when CS falls with CLK high. 7
Data Input Setup Time tSU 15 ns 7
Data Input Hold Time tHD 10 ns 7
SCK Rise to CS Rise Hold Time tCHS 15 ns 7
CS High Time tCSH 15 ns 7
LDAC Pulse Width tLD 100 ns 7
LDAC Setup Time tLS 40 ns 7
SCK Idle Time before CS Fall tIDLE 40 ns 7
Input Leakage Current ILEAKAGE -1 1 A SHDN = LDAC = CS = SDI = SCK + VREF = VDD or VSS 7
Specified Temperature Range TA -40 125 °C 8
Operating Temperature Range TA -40 125 °C 8
Storage Temperature Range TA -65 150 °C 8
Thermal Resistance, 14L-TSSOP JA 100 °C/W 8
VDD Supply Voltage (absolute maximum) VDD 6.5 V 3
All inputs and outputs w.r.t. VSS -0.3 V 3
Current at Input Pins -2 2 mA 3
Current at Supply Pins -50 50 mA 3
Current at Output Pins -25 25 mA 3
Ambient temp. with power applied TA -55 125 °C 3
Maximum Junction Temperature TJ 150 °C 3

CAD (KiCad official)

  • Symbol: MCP4902-E
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: mcp4902-e-etched.step / mcp4902-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp4902-e.step / mcp4902-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (48 pp, sha256 8c507a2bce321888, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF