component
MCP4901T-E
Public Made by Adomby adom
Microchip Tech Digital To Analog Converters (DAC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MCP4901T-E
Microchip Tech · Digital To Analog Converters (DAC) · SOIC-8
MCP4901T-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply voltage input, which must range from 2.7V to 5.5V relative to VSS; a 0.1 µF ceramic bypass capacitor with a 10 µF tantalum capacitor in parallel to ground is recommended. |
| 2 | CS | input | Active-low chip select input that must be asserted to enable the serial clock and data functions. |
| 3 | SCK | input | SPI-compatible serial clock input. |
| 4 | SDI | input | SPI-compatible serial data input. |
| 5 | LDAC | input | DAC synchronization input that transfers the input register to the output register (VOUT) when low; it can be tied to VSS so that VOUT updates on the rising edge of CS. |
| 6 | VREF | power_in | Voltage reference input for the resistive string DAC, with an allowed range from VSS to VDD; it can be tied to VDD. |
| 7 | VSS | power_in | Analog ground and current return path for the device, which must be connected to a ground plane through a low-impedance connection. |
| 8 | VOUT | output | DAC analog output from an output amplifier, with a full-scale range of VSS to G*VREF (G = 1x or 2x) that cannot exceed VDD. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Data Acquisition |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (VDD) absolute maximum | VDD | 6.5 | V | 3 | |||
| All inputs and outputs w.r.t. VSS (minimum) | -0.3 | V | W.r.t. VSS; printed maximum is VDD+0.3V | 3 | |||
| Current at input pins | -2 | 2 | mA | 3 | |||
| Current at supply pins | -50 | 50 | mA | 3 | |||
| Current at output pins | -25 | 25 | mA | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Ambient temperature with power applied | -55 | 125 | °C | 3 | |||
| Maximum junction temperature | TJ | 150 | °C | 3 | |||
| Input Voltage (operating supply) | VDD | 2.7 | 5.5 | V | 5 | ||
| Specified temperature range | TA | -40 | 125 | °C | 8 | ||
| Operating temperature range | TA | -40 | 125 | °C | Operation must not cause TJ to exceed 150°C (Note 1) | 8 | |
| INL error (MCP4901, extended temperature) | INL | -0.25 | 0.25 | LSb | 5 | ||
| DNL error (MCP4901, extended temperature) | DNL | -0.2 | 0.2 | LSb | Note 1 | 5 | |
| Offset error | VOS | -0.02 | 0.02 | % of FSR | Code = 0x000h | 5 | |
| Input range, buffered mode (VREF) | VREF | 0.04 | V | Buffered mode; printed upper limit VDD-0.040 V (Note 1) | 5 | ||
| Input range, unbuffered mode (VREF) | VREF | 0 | V | Unbuffered mode; printed upper limit VDD | 5 | ||
| Output swing | VOUT | 0.01 | V | Accuracy better than 1 LSb for VOUT = 10 mV to (VDD, 40 mV); printed upper limit VDD, 0.04 V | 6 | ||
| Schmitt trigger high level input voltage (all digital inputs) | VIH | 0.7 | × VDD | 7 | |||
| Schmitt trigger low level input voltage (all digital inputs) | VIL | 0.2 | × VDD | 7 | |||
| Input leakage current | ILEAKAGE | -1 | 1 | µA | LDAC = CS = SDI = SCK = VREF = VDD or VSS | 7 | |
| Clock frequency | FCLK | 20 | MHz | TA = +25°C (Note 1) | 7 | ||
| Clock high time | tHI | 15 | ns | Note 1 | 7 | ||
| Clock low time | tLO | 15 | ns | Note 1 | 7 | ||
| CS fall to first rising CLK edge | tCSSR | 40 | ns | Applies only when CS falls with CLK high (Note 1) | 7 | ||
| Data input setup time | tSU | 15 | ns | Note 1 | 7 | ||
| Data input hold time | tHD | 10 | ns | Note 1 | 7 | ||
| SCK rise to CS rise hold time | tCHS | 15 | ns | Note 1 | 7 | ||
| CS high time | tCSH | 15 | ns | Note 1 | 7 | ||
| LDAC pulse width | tLD | 100 | ns | Note 1 | 7 | ||
| LDAC setup time | tLS | 40 | ns | Note 1 | 7 | ||
| SCK idle time before CS fall | tIDLE | 40 | ns | Note 1 | 7 | ||
| Thermal resistance, junction to ambient, 8L-SOIC | θJA | 150 | °C/W | 8L-SOIC package | 8 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | MS = 8-Lead Plastic Micro Small Outline (MSOP) SN = 8-Lead Plastic Small Outline - Narrow, 150 mil | 47 |
CAD (KiCad official)
- Symbol:
MCP4901T-E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp4901t-e-etched.step/mcp4901t-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4901t-e.step/mcp4901t-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (50 pp, sha256
a52733deb49e0ae4, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).