component
MCP48FVB01-E
Public Made by Adomby adom
Microchip Tech Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MCP48FVB01-E
Microchip Tech · Digital To Analog Converters (DACs) · MSOP-10
MCP48FVB01-E from Microchip Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply voltage input, referenced to VSS; a 0.1 µF ceramic bypass to ground with an additional 10 µF tantalum in parallel is recommended. |
| 2 | CS | input | SPI chip select (Schmitt-trigger input) that enables or disables the serial interface, which must be enabled for SPI commands to be received. |
| 3 | VREF0 | bidirectional | Voltage reference input when the VREF pin is selected (buffered or unbuffered), or an output when the internal band gap is selected; with 2x gain the VREF voltage must be limited to a maximum of VDD/2. |
| 4 | VOUT0 | output | Buffered DAC analog voltage output with about 1 Ω DC output impedance in Normal mode; in Power-Down mode it is connected to a 1 kΩ or 100 kΩ pull-down or left open. |
| 5 | NC | unconnected | Not internally connected to the device. |
| 6 | LAT0/HVC | input | DAC register latch (high-voltage Schmitt-trigger input) that transfers the serial shift register value to the volatile DAC register, with HVC indicating voltage-level compatibility with the MCP48FEBXX nonvolatile family. |
| 7 | VSS | power_in | Ground reference for all circuitry on the device; must be connected to a ground plane through a low-impedance connection. |
| 8 | SDO | output | SPI serial data output used to read DAC registers and configuration bits. |
| 9 | SCK | input | SPI serial clock input (Schmitt trigger); the device accepts external serial clocks only. |
| 10 | SDI | input | SPI serial data input (Schmitt trigger) used to write DAC registers and configuration bits. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | MSOP-10 |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage on VDD with respect to VSS | -0.6 | 6.5 | V | 5 | |||
| Voltage on all pins with respect to VSS | -0.6 | V | 5 | ||||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0, VI > VDD, VI > VPP on HV pins | 5 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VDD | 5 | |
| Maximum current out of VSS pin (Single) | 50 | mA | Single | 5 | |||
| Maximum current into VDD pin (Single) | 50 | mA | Single | 5 | |||
| Maximum current sourced by the VOUT pin | 20 | mA | 5 | ||||
| Maximum current sunk by the VOUT pin | 20 | mA | 5 | ||||
| Maximum current sunk by the VREF pin | 125 | µA | 5 | ||||
| Maximum input current source/sunk by SDI, SCK, and CS pins | 2 | mA | 5 | ||||
| Maximum output current sunk by SDO pin | 25 | mA | 5 | ||||
| Total power dissipation | 400 | mW | 5 | ||||
| ESD protection on all pins (HBM) | -4 | 4 | kV | HBM | 5 | ||
| ESD protection on all pins (MM) | -400 | 400 | V | MM | 5 | ||
| ESD protection on all pins (CDM) | -1.5 | 1.5 | kV | CDM | 5 | ||
| Latch-Up | -100 | 100 | mA | Per JEDEC JESD78A @ +125°C | 5 | ||
| Storage temperature | -65 | 150 | °C | 5 | |||
| Ambient temperature with power applied | -55 | 125 | °C | 5 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 5 | |||
| Supply Voltage (full specifications) | VDD | 2.7 | 5.5 | V | 6 | ||
| Supply Voltage (reduced device specifications) | VDD | 1.8 | 2.7 | V | DAC operation (reduced analog specifications) and Serial Interface | 6 | |
| VDD Voltage (rising) to ensure device Power-on Reset | VPOR/BOR | 1.7 | V | RAM retention voltage (VRAM) < VPOR | 6 | ||
| High-Voltage Commands Voltage Range (HVC pin) | VHV | 12.5 | V | HVC pin | 6 | ||
| High-Voltage Input Entry Voltage | VIHHEN | 9 | V | Threshold for entry into WiperLock Technology | 6 | ||
| Power-on Reset to Output-Driven Delay | TPORD | 25 | 50 | µs | VDD rising, VDD > VPOR | 6 | |
| Supply Current, Single 1 MHz | IDD | 320 | µA | Serial interface active, VRxB:VRxA='01', VOUT unloaded, VDD=5.5V, DAC register=000h | 7 | ||
| Supply Current, Single 10 MHz | IDD | 910 | µA | Serial interface active, VRxB:VRxA='01', VOUT unloaded, VDD=5.5V, DAC register=000h | 7 | ||
| Supply Current, Single 20 MHz | IDD | 1.7 | mA | Serial interface active, VRxB:VRxA='01', VOUT unloaded, VDD=5.5V, DAC register=000h | 7 | ||
| Supply Current, Single 1 MHz (VREF mode) | IDD | 250 | µA | Serial interface active, VRxB:VRxA='10', VREF=VDD=5.5V, VOUT unloaded, DAC register=000h | 7 | ||
| Supply Current, Single 10 MHz (VREF mode) | IDD | 840 | µA | Serial interface active, VRxB:VRxA='10', VREF=VDD=5.5V, VOUT unloaded, DAC register=000h | 7 | ||
| Supply Current, Single 20 MHz (VREF mode) | IDD | 1.65 | mA | Serial interface active, VRxB:VRxA='10', VREF=VDD=5.5V, VOUT unloaded, DAC register=000h | 7 | ||
| Supply Current, Single serial interface inactive | IDD | 180 | µA | VRxB:VRxA='00', SCK=SDI=VSS, VOUT unloaded, DAC register=000h | 7 | ||
| Supply Current, Single serial interface inactive (VREF=VDD) | IDD | 180 | µA | VRxB:VRxA='11', VREF=VDD, SCK=SDI=VSS, VOUT unloaded, DAC register=000h | 7 | ||
| Supply Current, Single High-Voltage Command | IDD | 145 | 180 | µA | HVC=12.5V, serial interface inactive, VREF=VDD=5.5V, LAT/HVC=VIHH, DAC registers=000h, VOUT unloaded | 7 | |
| Power-Down Current | IDDP | 0.65 | 3.8 | µA | PDxB:PDxA='01', VOUT not connected | 7 | |
| Resistor Ladder Resistance | RL | 100 | 140 | 180 | kΩ | 1.8V ≤ VDD ≤ 5.5V, VREF ≤ 1.0V | 8 |
| Nominal VOUT Match | /VOUT - VOUTMEAN//VOUTMEAN | 0.5 | 1 | % | 2.7V ≤ VDD ≤ 5.5V | 8 | |
| Nominal VOUT Match (1.8V) | /VOUT - VOUTMEAN//VOUTMEAN | 1.2 | % | 1.8V | 8 | ||
| Power Supply Sensitivity | PSS | 0.002 | 0.005 | %/% | 8-bit Code = 7Fh | 16 | |
| Band Gap Voltage | VBG | 1.18 | 1.22 | 1.26 | V | 14 | |
| Short-Circuit Current | ISC | 3 | 9 | 14 | mA | DAC code = Full Scale | 14 |
| Operating Range (VDD) - VREF pin voltage stable | VDD | 2 | V | VREF pin voltage stable | 14 | ||
| Operating Range (VDD) - VOUT output linear | VDD | 2.2 | V | VOUT output linear | 14 | ||
| Input Leakage Current | IIL | -1 | 1 | µA | VIN = VDD and VIN = VSS | 15 | |
| CS active (VIL) to command's 1st SCK input | TcsA2scH | 60 | ns | Mode 11 | 21 | ||
| SCK input frequency (read command) | FSCK | 10 | MHz | Read command, VDD = 2.7V to 5.5V, Mode 11 | 21 | ||
| SCK input frequency (all other commands) | FSCK | 20 | MHz | All other commands, VDD = 2.7V to 5.5V, Mode 11 | 21 | ||
| SCK input high time | TscH | 20 | ns | VDD = 2.7V to 5.5V | 21 | ||
| SCK input low time | TscL | 20 | ns | VDD = 2.7V to 5.5V | 21 | ||
| Setup time of SDI input to SCK edge | TdiV2scH | 10 | ns | 21 | |||
| Hold time of SDI input from SCK edge | TscH2diL | 20 | ns | 21 | |||
| CS Inactive (VIH) to SDO output hi-impedance | TcsH2DOZ | 50 | ns | Note 1 (ensured by design) | 21 | ||
| SDO data output valid after SCK edge | TscL2doV | 45 | ns | VDD = 2.7V to 5.5V | 21 | ||
| CS Inactive (VIH) after SCK edge | TscH2csL | 100 | ns | VDD = 2.7V to 5.5V | 21 | ||
| CS high time (VIH) | TcsH | 50 | ns | 21 | |||
| LAT to SCK↑ (write data 24th bit) setup time | TLATSU | 20 | ns | Write data transferred | 21 | ||
| LAT high or low time | TLAT | 20 | ns | 21 | |||
| HVC to SCK (1st data bit) setup time | THVCSU | 0 | ns | High-Voltage Commands (MCP48FEBxx only) | 21 | ||
| SCK ↑ (last bit) to HVC hold time | THVCHD | 25 | ns | High-Voltage Commands (MCP48FEBxx only) | 21 |
CAD (KiCad official)
- Symbol:
MCP48FVB01-E - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
mcp48fvb01-e-etched.step/mcp48fvb01-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp48fvb01-e.step/mcp48fvb01-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (84 pp, sha256
890ee51a261bf226, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP48FVB01-E
**Microchip Tech** · Digital To Analog Converters (DACs) · MSOP-10
MCP48FVB01-E from Microchip Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply voltage input, referenced to VSS; a 0.1 µF ceramic bypass to ground with an additional 10 µF tantalum in parallel is recommended. |
| 2 | CS | input | SPI chip select (Schmitt-trigger input) that enables or disables the serial interface, which must be enabled for SPI commands to be received. |
| 3 | VREF0 | bidirectional | Voltage reference input when the VREF pin is selected (buffered or unbuffered), or an output when the internal band gap is selected; with 2x gain the VREF voltage must be limited to a maximum of VDD/2. |
| 4 | VOUT0 | output | Buffered DAC analog voltage output with about 1 Ω DC output impedance in Normal mode; in Power-Down mode it is connected to a 1 kΩ or 100 kΩ pull-down or left open. |
| 5 | NC | unconnected | Not internally connected to the device. |
| 6 | LAT0/HVC | input | DAC register latch (high-voltage Schmitt-trigger input) that transfers the serial shift register value to the volatile DAC register, with HVC indicating voltage-level compatibility with the MCP48FEBXX nonvolatile family. |
| 7 | VSS | power_in | Ground reference for all circuitry on the device; must be connected to a ground plane through a low-impedance connection. |
| 8 | SDO | output | SPI serial data output used to read DAC registers and configuration bits. |
| 9 | SCK | input | SPI serial clock input (Schmitt trigger); the device accepts external serial clocks only. |
| 10 | SDI | input | SPI serial data input (Schmitt trigger) used to write DAC registers and configuration bits. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | MSOP-10 |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage on VDD with respect to VSS | | -0.6 | | 6.5 | V | | 5 |
| Voltage on all pins with respect to VSS | | -0.6 | | | V | | 5 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < 0, VI > VDD, VI > VPP on HV pins | 5 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < 0 or VO > VDD | 5 |
| Maximum current out of VSS pin (Single) | | | | 50 | mA | Single | 5 |
| Maximum current into VDD pin (Single) | | | | 50 | mA | Single | 5 |
| Maximum current sourced by the VOUT pin | | | | 20 | mA | | 5 |
| Maximum current sunk by the VOUT pin | | | | 20 | mA | | 5 |
| Maximum current sunk by the VREF pin | | | | 125 | µA | | 5 |
| Maximum input current source/sunk by SDI, SCK, and CS pins | | | | 2 | mA | | 5 |
| Maximum output current sunk by SDO pin | | | | 25 | mA | | 5 |
| Total power dissipation | | | | 400 | mW | | 5 |
| ESD protection on all pins (HBM) | | -4 | | 4 | kV | HBM | 5 |
| ESD protection on all pins (MM) | | -400 | | 400 | V | MM | 5 |
| ESD protection on all pins (CDM) | | -1.5 | | 1.5 | kV | CDM | 5 |
| Latch-Up | | -100 | | 100 | mA | Per JEDEC JESD78A @ +125°C | 5 |
| Storage temperature | | -65 | | 150 | °C | | 5 |
| Ambient temperature with power applied | | -55 | | 125 | °C | | 5 |
| Maximum Junction Temperature | TJ | | | 150 | °C | | 5 |
| Supply Voltage (full specifications) | VDD | 2.7 | | 5.5 | V | | 6 |
| Supply Voltage (reduced device specifications) | VDD | 1.8 | | 2.7 | V | DAC operation (reduced analog specifications) and Serial Interface | 6 |
| VDD Voltage (rising) to ensure device Power-on Reset | VPOR/BOR | | | 1.7 | V | RAM retention voltage (VRAM) < VPOR | 6 |
| High-Voltage Commands Voltage Range (HVC pin) | VHV | | | 12.5 | V | HVC pin | 6 |
| High-Voltage Input Entry Voltage | VIHHEN | 9 | | | V | Threshold for entry into WiperLock Technology | 6 |
| Power-on Reset to Output-Driven Delay | TPORD | | 25 | 50 | µs | VDD rising, VDD > VPOR | 6 |
| Supply Current, Single 1 MHz | IDD | | | 320 | µA | Serial interface active, VRxB:VRxA='01', VOUT unloaded, VDD=5.5V, DAC register=000h | 7 |
| Supply Current, Single 10 MHz | IDD | | | 910 | µA | Serial interface active, VRxB:VRxA='01', VOUT unloaded, VDD=5.5V, DAC register=000h | 7 |
| Supply Current, Single 20 MHz | IDD | | | 1.7 | mA | Serial interface active, VRxB:VRxA='01', VOUT unloaded, VDD=5.5V, DAC register=000h | 7 |
| Supply Current, Single 1 MHz (VREF mode) | IDD | | | 250 | µA | Serial interface active, VRxB:VRxA='10', VREF=VDD=5.5V, VOUT unloaded, DAC register=000h | 7 |
| Supply Current, Single 10 MHz (VREF mode) | IDD | | | 840 | µA | Serial interface active, VRxB:VRxA='10', VREF=VDD=5.5V, VOUT unloaded, DAC register=000h | 7 |
| Supply Current, Single 20 MHz (VREF mode) | IDD | | | 1.65 | mA | Serial interface active, VRxB:VRxA='10', VREF=VDD=5.5V, VOUT unloaded, DAC register=000h | 7 |
| Supply Current, Single serial interface inactive | IDD | | | 180 | µA | VRxB:VRxA='00', SCK=SDI=VSS, VOUT unloaded, DAC register=000h | 7 |
| Supply Current, Single serial interface inactive (VREF=VDD) | IDD | | | 180 | µA | VRxB:VRxA='11', VREF=VDD, SCK=SDI=VSS, VOUT unloaded, DAC register=000h | 7 |
| Supply Current, Single High-Voltage Command | IDD | | 145 | 180 | µA | HVC=12.5V, serial interface inactive, VREF=VDD=5.5V, LAT/HVC=VIHH, DAC registers=000h, VOUT unloaded | 7 |
| Power-Down Current | IDDP | | 0.65 | 3.8 | µA | PDxB:PDxA='01', VOUT not connected | 7 |
| Resistor Ladder Resistance | RL | 100 | 140 | 180 | kΩ | 1.8V ≤ VDD ≤ 5.5V, VREF ≤ 1.0V | 8 |
| Nominal VOUT Match | /VOUT - VOUTMEAN//VOUTMEAN | | 0.5 | 1 | % | 2.7V ≤ VDD ≤ 5.5V | 8 |
| Nominal VOUT Match (1.8V) | /VOUT - VOUTMEAN//VOUTMEAN | | | 1.2 | % | 1.8V | 8 |
| Power Supply Sensitivity | PSS | | 0.002 | 0.005 | %/% | 8-bit Code = 7Fh | 16 |
| Band Gap Voltage | VBG | 1.18 | 1.22 | 1.26 | V | | 14 |
| Short-Circuit Current | ISC | 3 | 9 | 14 | mA | DAC code = Full Scale | 14 |
| Operating Range (VDD) - VREF pin voltage stable | VDD | 2 | | | V | VREF pin voltage stable | 14 |
| Operating Range (VDD) - VOUT output linear | VDD | 2.2 | | | V | VOUT output linear | 14 |
| Input Leakage Current | IIL | -1 | | 1 | µA | VIN = VDD and VIN = VSS | 15 |
| CS active (VIL) to command's 1st SCK input | TcsA2scH | 60 | | | ns | Mode 11 | 21 |
| SCK input frequency (read command) | FSCK | | | 10 | MHz | Read command, VDD = 2.7V to 5.5V, Mode 11 | 21 |
| SCK input frequency (all other commands) | FSCK | | | 20 | MHz | All other commands, VDD = 2.7V to 5.5V, Mode 11 | 21 |
| SCK input high time | TscH | 20 | | | ns | VDD = 2.7V to 5.5V | 21 |
| SCK input low time | TscL | 20 | | | ns | VDD = 2.7V to 5.5V | 21 |
| Setup time of SDI input to SCK edge | TdiV2scH | 10 | | | ns | | 21 |
| Hold time of SDI input from SCK edge | TscH2diL | 20 | | | ns | | 21 |
| CS Inactive (VIH) to SDO output hi-impedance | TcsH2DOZ | | | 50 | ns | Note 1 (ensured by design) | 21 |
| SDO data output valid after SCK edge | TscL2doV | | | 45 | ns | VDD = 2.7V to 5.5V | 21 |
| CS Inactive (VIH) after SCK edge | TscH2csL | 100 | | | ns | VDD = 2.7V to 5.5V | 21 |
| CS high time (VIH) | TcsH | 50 | | | ns | | 21 |
| LAT to SCK↑ (write data 24th bit) setup time | TLATSU | 20 | | | ns | Write data transferred | 21 |
| LAT high or low time | TLAT | 20 | | | ns | | 21 |
| HVC to SCK (1st data bit) setup time | THVCSU | 0 | | | ns | High-Voltage Commands (MCP48FEBxx only) | 21 |
| SCK ↑ (last bit) to HVC hold time | THVCHD | 25 | | | ns | High-Voltage Commands (MCP48FEBxx only) | 21 |
## CAD (KiCad official)
- Symbol: `MCP48FVB01-E`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files: `mcp48fvb01-e-etched.step` / `mcp48fvb01-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp48fvb01-e.step` / `mcp48fvb01-e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/mcp48fvb01-e-datasheet.pdf) (84 pp, sha256 `890ee51a261bf226`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp48fvb01-e-datasheet.pdf)