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docs mcp4821: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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mcp4821-etched.fit.json mcp4821: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
mcp4821-etched.glb mcp4821: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
mcp4821-etched.step mcp4821: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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README.md mcp4821: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

MCP4821

Microchip · Digital-to-Analog Converter · MSOP-8

The MCP4821 is a single-channel, 12-bit voltage-output DAC with an internal 2.048 V reference and an SPI interface. The on-chip reference and selectable output gain mean it needs no external reference to produce a precise analog voltage, suiting set-point generation, bias control, and programmable voltage sources.

Pinout

Pin Name Type Function
1 VDD power_in Positive supply voltage input, 2.7 V to 5.5 V relative to VSS. Bypass with 0.1 µF ceramic to VSS close to the pin, plus a 10 µF tantalum in parallel for board-level noise attenuation.
2 CS input Active-low SPI chip-select input. Must be driven low to enable the serial clock and data functions; the DAC latches on the rising edge of CS.
3 SCK input SPI-compatible serial clock input. Supports SPI Modes 0,0 and 1,1 with clock rates up to 20 MHz.
4 SDI input SPI-compatible serial data input. Command/data word (16 bits) is shifted in MSb-first while CS is low.
5 LDAC input Active-low latch-DAC synchronization input. Transfers input register contents to the DAC output registers (VOUT) on its falling edge, allowing simultaneous update of both channels. May be tied to VSS to update on the rising edge of CS.
6 SHDN output Shutdown control input, active low. When held low, the DAC output goes to a high-impedance state and the device enters low-power shutdown.
7 VSS power_in Analog ground and return path for the device. Tie to the board's analog ground plane through a low-impedance connection.
8 VOUT output Buffered analog output of DAC channel A. Rail-to-rail swing from VSS to G·VREF (G = 1x or 2x); cannot exceed VDD. Uses the internal 2.048 V reference so full-scale is 2.048 V (G=1x) or 4.096 V (G=2x).

Key specifications

Parameter Value
Resolution 12-bit, 1 channel
Output Voltage output (buffered, rail-to-rail)
Reference Internal 2.048 V, 1x or 2x gain
Interface SPI (up to 20 MHz)
Settling time 4.5 us typ
Supply voltage 2.7 V to 5.5 V
Operating temperature -40 C to 125 C

Ordering variants

Same part, different packaging or reel option.

  • MCP4821I/P
  • MCP4821E/P
  • MCP4821I/SN
  • MCP4821E/SN
  • MCP4821I/MS
  • MCP4821E/MS

CAD (KiCad official)

  • Symbol: mcp4821.kicad_sym
  • Footprint: mcp4821.kicad_mod
  • 3D model: MSOP-8 body from KiCad Package_SO/MSOP-8_3x3mm_P0.65mm.
  • 3D model files: mcp4821-etched.step / mcp4821-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp4821.step / mcp4821.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip datasheet (50 pp, sha256 1f0b231636222ea5, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF