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MCP4821-E
Public Made by Adomby adom
Microchip Tech Digital To Analog Converters (DAC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownMCP4821-E
Microchip Tech · Digital To Analog Converters (DAC) · SOIC-8
MCP4821-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply voltage input, which can range from 2.7V to 5.5V relative to VSS; a 0.1 µF ceramic bypass capacitor to ground, with an additional 10 µF tantalum in parallel, is recommended. |
| 2 | CS | input | Chip Select input that requires an active low to enable the serial clock and data functions. |
| 3 | SCK | input | SPI compatible serial clock input. |
| 4 | SDI | input | SPI compatible serial data input. |
| 5 | LDAC | input | DAC output synchronization input that, when low, transfers the input register contents to the output register so VOUT is updated; it can be tied to VSS to update VOUT on the rising edge of CS. |
| 6 | SHDN | input | Hardware Shutdown input used to place the device in Shutdown mode, in which most internal circuits including the output amplifier are turned off and VOUT is presented with a known high-resistance load. |
| 7 | VSS | power_in | Ground reference point and analog ground/current return for all circuitry; it must be connected to a ground plane through a low-impedance connection. |
| 8 | VOUT | output | DAC analog output with an output amplifier; the full-scale range is VSS to G×VREF (G = 1x or 2x) and it cannot go higher than VDD. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Data Acquisition |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Voltage | VDD | 2.7 | 5.5 | V | 3 | ||
| Operating Current | IDD | 330 | 400 | µA | All digital inputs are grounded, analog output (VOUT) is unloaded. Code = 000h | 3 | |
| Hardware Shutdown Current | ISHDN | 0.3 | 2 | µA | POR circuit is turned off | 3 | |
| Software Shutdown Current | ISHDN_SW | 3.3 | 6 | µA | POR circuit remains turned on | 3 | |
| Resolution (MCP4821) | n | 12 | Bits | 3 | |||
| INL Error (MCP4821) | INL | -12 | 2 | 12 | LSb | 3 | |
| DNL (MCP4821) | DNL | -0.75 | 0.2 | 0.75 | LSb | Note 1: Guaranteed monotonic by design over all codes. | 3 |
| Offset Error | VOS | -1 | 0.02 | 1 | % of FSR | Code = 0x000h | 3 |
| Gain Error | gE | -2 | -0.1 | 2 | % of FSR | Code = 0xFFFh, not including offset error | 3 |
| Internal Reference Voltage | VREF | 2.008 | 2.048 | 2.088 | V | VOUT when G = 1x and Code = 0xFFFh | 4 |
| VREF Temperature Coefficient | VREF/°C | 125 | 325 | ppm/°C | -40°C to 0°C | 4 | |
| VREF Temperature Coefficient | VREF/°C | 0.25 | 0.65 | LSb/°C | -40°C to 0°C | 4 | |
| VREF Temperature Coefficient | VREF/°C | 45 | 160 | ppm/°C | 0°C to +85°C | 4 | |
| VREF Temperature Coefficient | VREF/°C | 0.09 | 0.32 | LSb/°C | 0°C to +85°C | 4 | |
| Output Swing | VOUT | 0.01 | V | Accuracy better than 1 LSb for VOUT = 10 mV to (VDD, 40 mV); printed range 0.01 to VDD, 0.04 | 4 | ||
| Short Circuit Current | ISC | 15 | 24 | mA | 4 | ||
| Schmitt Trigger High-Level Input Voltage (all digital inputs) | VIH | 0.7 | VDD | 6 | |||
| Schmitt Trigger Low-Level Input Voltage (all digital inputs) | VIL | 0.2 | VDD | 6 | |||
| Input Leakage Current | ILEAKAGE | -1 | 1 | A | SHDN = LDAC = CS = SDI = SCK = VDD or VSS | 6 | |
| Clock Frequency | FCLK | 20 | MHz | TA = +25°C (Note 1) | 6 | ||
| Clock High Time | tHI | 15 | ns | Note 1: ensured by design, not 100% tested | 6 | ||
| Clock Low Time | tLO | 15 | ns | Note 1: ensured by design, not 100% tested | 6 | ||
| CS Fall to First Rising CLK Edge | tCSSR | 40 | ns | Applies only when CS falls with CLK high. (Note 1) | 6 | ||
| Data Input Setup Time | tSU | 15 | ns | Note 1: ensured by design, not 100% tested | 6 | ||
| Data Input Hold Time | tHD | 10 | ns | Note 1: ensured by design, not 100% tested | 6 | ||
| SCK Rise to CS Rise Hold Time | tCHS | 15 | ns | Note 1: ensured by design, not 100% tested | 6 | ||
| CS High Time | tCSH | 15 | ns | Note 1: ensured by design, not 100% tested | 6 | ||
| LDAC Pulse Width | tLD | 100 | ns | Note 1: ensured by design, not 100% tested | 6 | ||
| LDAC Setup Time | tLS | 40 | ns | Note 1: ensured by design, not 100% tested | 6 | ||
| SCK Idle Time before CS Fall | tIDLE | 40 | ns | Note 1: ensured by design, not 100% tested | 6 | ||
| Specified Temperature Range | TA | -40 | 125 | °C | 7 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | Note 1: reduced performance; TJ must not exceed +150°C | 7 | |
| Storage Temperature Range | TA | -65 | 150 | °C | 7 | ||
| Thermal Resistance, 8L-SOIC | θJA | 150 | °C/W | 7 | |||
| VDD Supply Voltage (absolute maximum) | VDD | 6.5 | V | 3 | |||
| All Inputs and Outputs Voltage | VIN/VOUT | -0.3 | V | Referenced to VSS; upper limit printed as VDD + 0.3V | 3 | ||
| Current at Input Pins | IIN | -2 | 2 | mA | 3 | ||
| Current at Supply Pins | ISUP | -50 | 50 | mA | 3 | ||
| Current at Output Pins | IOUT | -25 | 25 | mA | 3 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 3 | ||
| Ambient Temperature with Power Applied | TA | -55 | 125 | °C | 3 | ||
| Maximum Junction Temperature | TJ | 150 | °C | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | P = 8-Lead Plastic Dual In-Line (PDIP) SN = 8-Lead Plastic Small Outline - Narrow, 150 mil | 45 |
CAD (KiCad official)
- Symbol:
MCP4821-E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp4821-e-etched.step/mcp4821-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4821-e.step/mcp4821-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (48 pp, sha256
e4bf1d222bf746ef, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).