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MCP47CVB02-E

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Microchip Tech Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionmcp47cvb02-efactory-2.0.0extractor-text

Verified MCP47CVB02-E

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 10 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: MCP47CVB02-E · MSOP-10 · 10 pins
  • ✓copper: 10 copper pads, none touching another net
  • ✓datasheet: all 10 pin names found in the 124-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: MSOP-10_3x3mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-sm0uhy2l/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 10 pins = 10 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 10 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ mcp47cvb02-e.kicad_sym✓ mcp47cvb02-e.kicad_mod✓ mcp47cvb02-e.step
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MCP47CVB02-E

Microchip Tech · Digital To Analog Converters (DACs) · MSOP-10

MCP47CVB02-E from Microchip Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Positive supply voltage input, referenced to VSS; full specifications apply from 2.7V to 5.5V, reduced specifications from 1.8V to 2.7V, and a ~0.1 µF ceramic bypass capacitor is recommended close to the pin.
2 A0 input I2C slave address bit 0 input (Schmitt trigger) that, together with A1, sets the lower two bits of the I2C slave address.
3 VREF power_in Analog voltage reference pin that is an input when the DAC reference is the external VREF (buffered or unbuffered) and an output when the reference is the internal band gap (1.214V typical), in which case the output should be buffered.
4 VOUT0 output Buffered analog voltage output of DAC0, with full-scale range from VSS to approximately VDD (device VDD reference) or G x VREF / G x VBG, where G is the selected gain of 1x or 2x.
5 VOUT1 output Buffered analog voltage output of DAC1, with full-scale range from VSS to approximately VDD (device VDD reference) or G x VREF / G x VBG, where G is the selected gain of 1x or 2x.
6 LAT/HVC input Level-sensitive DAC latch input that transfers volatile wiper and configuration values to both DAC outputs when pulled to VIL, and carries the high-voltage MTP programming supply (7.5V, at least 6.4 mA) which must not exceed 5.5V except during programming.
7 VSS power_in Ground reference pin for all circuitry on the device, to be connected through a low-impedance path to the ground plane.
8 A1 input I2C slave address bit 1 input (Schmitt trigger) that, together with A0, sets the lower two bits of the I2C slave address.
9 SCL input I2C serial clock input (Schmitt trigger); the device operates as a slave, does not generate the clock, and does not stretch it.
10 SDA bidirectional I2C serial data input/output (Schmitt trigger) with slope control implemented on the output driver.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package MSOP-10
Category ADC/DAC/Data Conversion
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD 2.7 5.5 V 6
Supply Voltage, reduced analog specifications VDD 1.8 2.7 V DAC operation (reduced analog specifications) and serial interface 6
VDD Voltage (rising) to Ensure Device Power-on Reset VPOR 1.75 V RAM retention voltage: (VRAM)<VPOR 6
VDD Voltage (falling) to Ensure Device Brown-out Reset VBOR 1.61 V RAM retention voltage: (VRAM)<VBOR 6
Power-on Reset to Output-Driven Delay, dual output TPOR2OD 145 µs VDD rising, VDD >VPOR, dual output 6
Supply Current, dual, 100 kHz IDD 330 µA Dual 100 kHz; serial interface active, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, volatile DAC register = Mid-Scale 7
Supply Current, dual, 400 kHz IDD 410 µA Dual 400 kHz; serial interface active, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, volatile DAC register = Mid-Scale 7
Supply Current, dual, 1.7 MHz IDD 560 µA Dual 1.7 MHz; serial interface active, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, volatile DAC register = Mid-Scale 7
Supply Current, dual, 3.4 MHz IDD 720 µA Dual 3.4 MHz; serial interface active, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, volatile DAC register = Mid-Scale 7
Supply Current, dual, serial interface inactive IDD 280 µA Dual; serial interface inactive, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, volatile DAC register = Mid-Scale 7
Power-Down Current IDDP 0.65 3.8 µA PDxB:PDxA = 01, VRxB:VRxA = 10, VOUT not connected 7
Resistor Ladder Resistance RL 63.9 71 78.1 kΩ VRxB:VRxA = 10, VREF = VDD 8
Nominal VOUT Match, dual devices /VOUT, VOUTMEAN//VOUTMEAN 0.016 0.3 % 1.8V ≤ VDD ≤ 5.5V 8
Zero-Scale Error, 8-bit EZS 0.375 LSb 8-bit, VRxB:VRxA = 10, G = 0, VREF = VDD, no load 9
Offset Error EOS -6 0.4 6 mV VRxB:VRxA = 10, Gx = 0, no load, 8-bit: Code = 4 9
Offset Voltage Temperature Coefficient VOSTC -5 5 µV/°C 9
Full-Scale Error, 8-bit EFS 2.5 LSb 8-bit, VRxB:VRxA = 10, G = 0, VREF = VDD, no load 9
Gain Error EG -1 0.1 1 % of FSR 8-bit, VRxB:VRxA = 10, G = 0, Code = 252, VREF = VDD, no load 9
Total Unadjusted Error, 8-bit ET -2.5 0.75 LSb 8-bit, VRxB:VRxA = 10, G = 0, VREF = VDD, no load 10
Integral Nonlinearity, 8-bit INL -0.1 0.1 LSb 8-bit, VRxB:VRxA = 10, G = 0, VREF = VDD, no load 10
Differential Nonlinearity, 8-bit DNL -0.1 0.1 LSb 8-bit, VRxB:VRxA = 10, G = 0, VREF = VDD, no load 10
Short-Circuit Current, output amplifier, short to VSS ISC_OA 6 10 14 mA Short to VSS, DAC code = Full Scale 11
Short-Circuit Current, output amplifier, short to VDD ISC_OA 6 10 14 mA Short to VDD, DAC code = Zero Scale 11
Band Gap Voltage VBG 1.18 1.214 1.26 V 1.8V ≤ VDD ≤ 5.5V 11
Short-Circuit Current, band gap, short to VSS ISC_BG 6 10 14 mA Short to VSS 11
Short-Circuit Current, band gap, short to VDD ISC_BG 6 10 14 mA Short to VDD 11
Current through VREF IVREF 172.15 µA Mathematically from RVREF(min) spec (at 5.5V) 12
Schmitt Trigger High Input Threshold, LAT0/HVC, LAT1, A0, A1 VIH 0.45 VDD 1.8V ≤ VDD ≤ 5.5V (allows 2.7V digital VDD with 5.5V analog VDD or 1.8V digital VDD with 3.0V analog VDD) 13
Schmitt Trigger Low Input Threshold, LAT0/HVC, LAT1, A0, A1 VIL 0.2 VDD 13
Input Leakage Current, LAT0/HVC, LAT1, A0, A1 IIL -1 1 µA VIN = VDD and VIN = VSS 13
Output Low Voltage, SDA VOL 0.4 V VDD ≥ 2.0V, IOL = 3 mA 13
Output Low Voltage, SDA, low VDD VOL 0.2 VDD VDD < 2.0V, IOL = 1 mA 13
Input High Voltage, SDA and SCL VIH 0.7 VDD 1.8V ≤ VDD ≤ 5.5V 13
Input Low Voltage, SDA and SCL VIL 0.3 VDD 1.8V ≤ VDD ≤ 5.5V 13
Input Leakage, SDA and SCL IL -1 1 µA SCL = SDA = VSS or SCL = SDA = VDD 13
LATx Pin Pulse Width tLAT 20 ns 16
Power-on Reset Delay, dual tPOR2SIA 145 µs Dual; monitor ACK bit response to ensure the device responds to command 17
SCL Pin Frequency, Standard mode FSCL 0 100 kHz Standard mode; Cb = 400 pF, 1.8V-5.5V 18
SCL Pin Frequency, Fast mode FSCL 0 400 kHz Fast mode; Cb = 400 pF, 2.7V-5.5V 18
SCL Pin Frequency, High Speed 1.7 FSCL 0 1.7 MHz High Speed 1.7; Cb = 400 pF, 4.5V-5.5V 18
SCL Pin Frequency, High Speed 3.4 FSCL 0 3.4 MHz High Speed 3.4; Cb = 100 pF, 4.5V-5.5V 18
Voltage on VDD with respect to VSS VDD -0.6 6.5 V 5
Voltage on all pins with respect to VSS -0.6 V Printed maximum is VDD + 0.3V 5
Input clamp current IIK -20 20 mA VI < 0, VI > VDD, VI > VPP on HV pins 5
Maximum current out of VSS pin, dual 100 mA Dual device 5
Maximum current into VDD pin, dual 100 mA Dual device 5
Maximum current sourced by the VOUT pin 20 mA 5
Maximum current sunk by the VOUT pin 20 mA 5
Maximum current source/sunk by the VREF(0) pin 20 mA In Band Gap mode 5
Maximum current sourced by the VREFx pin 20 µA 5
Maximum current sunk by the VREF pin 125 µA 5
Maximum input current source/sunk by SDA, SCL pins 2 mA 5
Maximum output current sunk by SDA output pin 25 mA 5
Total power dissipation 400 mW 5
ESD protection on all pins, HBM -6 6 kV HBM 5
Storage temperature -65 150 °C 5
Ambient temperature with power applied -55 125 °C 5
Maximum junction temperature TJ 150 °C 5
Operating ambient temperature (Extended) TA -40 125 °C Standard Operating Conditions, extended temperature range 6

CAD (KiCad official)

  • Symbol: MCP47CVB02-E
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: mcp47cvb02-e-etched.step / mcp47cvb02-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp47cvb02-e.step / mcp47cvb02-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (124 pp, sha256 00ea6d555e34c774, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF