component
MCP4726A2T-E
Public Made by Adomby adom
Microchip Tech Digital To Analog Converters (DAC), SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MCP4726A2T-E
Microchip Tech · Digital To Analog Converters (DAC) · SOT-23-6
MCP4726A2T-E from Microchip Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | Buffered analog DAC voltage output that swings from approximately 0V to approximately VDD, with a full-scale range of VSS to G × VREF and about 1Ω DC output impedance in Normal mode. |
| 2 | VSS | power_in | Ground reference pin for all circuitry on the device, which must be connected to a low-impedance ground plane. |
| 3 | VDD | power_in | Positive supply voltage input, relative to VSS, specified for 2.7V to 5.5V operation and recommended to be bypassed with about 0.1 µF ceramic plus 10 µF tantalum capacitors. |
| 4 | SDA | bidirectional | I2C serial data pin, an open-drain N-channel driver that requires a pull-up resistor from VDD and must only change state while SCL is low (except for Start and Stop conditions). |
| 5 | SCL | input | I2C serial clock input that accepts only external clocks from the master, with an open-drain N-channel driver that requires a pull-up resistor from VDD. |
| 6 | VREF | power_in | External voltage reference input that can be selected as the resistor ladder reference instead of VDD, optionally buffered, and limited to a maximum of VDD/2 when the output gain is 2. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOT-23-6 |
| Category | Data Acquisition |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VDD | 2.7 | 5.5 | V | 4 | ||
| Input Current | IDD | 210 | 400 | µA | VREF1:VREF0 = 00, SCL = SDA = VSS, VOUT is unloaded, volatile DAC Register = 0x000 | 4 | |
| Power-Down Current | IDDP | 0.09 | 2 | µA | PD1:PD0 = 01 (Note 6), VOUT not connected | 4 | |
| Power-Up Ramp Rate | VRAMP | 1 | V/S | Note 1, Note 4 | 4 | ||
| Offset Error | VOS | 0.02 | 0.75 | % of FSR | Code = 0x000h, VREF1:VREF0 = 00, G = 0 | 4 | |
| Zero-Scale Error | EZS | 2.05 | 30.8 | LSb | MCP4726, Code = 0x000h | 4 | |
| Full-Scale Error | EFS | 4.1 | 82 | LSb | MCP4726, Code = 0xFFFh | 4 | |
| Gain Error | gE | -2 | -0.1 | 2 | % of FSR | MCP4726, Code = 0xFFFh, VREF1:VREF0 = 00, G = 0; Note 2 | 4 |
| INL Error | INL | -14.5 | 2 | 14.5 | LSb | MCP4726 (codes: 100 to 4000); Note 7: VDD = VREF = 5.5V | 4 |
| DNL Error | DNL | -0.75 | 0.2 | 0.75 | LSb | MCP4726 (codes: 100 to 4000); Note 7: VDD = VREF = 5.5V | 4 |
| Short Circuit Current | ISC | 7 | 15 | 24 | mA | 5 | |
| External Reference Input Range (buffered mode) | VREF | 0.04 | V | Buffered mode | 5 | ||
| External Reference Input Range (unbuffered mode) | VREF | 0 | V | Unbuffered mode | 5 | ||
| Output Low Voltage | VOL | 0.4 | V | IOL = 3 mA | 6 | ||
| Input Leakage | ILI | -1 | 1 | µA | SCL = SDA = VSS or SCL = SDA = VDD | 6 | |
| Pin Capacitance | CPIN | 3 | pF | Note 5 | 6 | ||
| EEPROM Write Time | TWRITE | 25 | 50 | ms | 6 | ||
| Endurance | 1 | Million Cycles | At +25°C, Note 1 | 6 | |||
| Voltage on VDD with respect to VSS | VDD | -0.6 | 6.5 | V | 3 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0, VI > VDD | 3 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VDD | 3 | |
| Maximum input current source/sunk by SDA, SCL pins | 2 | mA | 3 | ||||
| Maximum output current sunk by SDA Output pin | 25 | mA | 3 | ||||
| Maximum current out of VSS pin | 50 | mA | 3 | ||||
| Maximum current into VDD pin | 50 | mA | 3 | ||||
| Maximum current sourced by the VOUT pin | 40 | mA | 3 | ||||
| Maximum current sunk by the VOUT pin | 40 | mA | 3 | ||||
| Maximum current sunk by the VREF pin | 40 | µA | 3 | ||||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Ambient temperature with power applied | -55 | 125 | °C | 3 | |||
| ESD protection on all pins (HBM) | 6 | kV | HBM | 3 | |||
| ESD protection on all pins (MM) | 400 | V | MM | 3 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 3 | |||
| Specified Temperature Range | TA | -40 | 125 | °C | 13 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | Note 1 | 13 | |
| Thermal Resistance, 6L-SOT-23 | θJA | 190 | °C/W | 13 | |||
| SCL pin Frequency (Standard mode) | FSCL | 0 | 100 | kHz | Cb = 400 pF, 2.7V - 5.5V | 8 | |
| SCL pin Frequency (Fast mode) | FSCL | 0 | 400 | kHz | Cb = 400 pF, 2.7V - 5.5V | 8 | |
| SCL pin Frequency (High-Speed 1.7 MHz) | FSCL | 0 | 1.7 | MHz | Cb = 400 pF, 4.5V - 5.5V | 8 | |
| SCL pin Frequency (High-Speed 3.4 MHz) | FSCL | 0 | 3.4 | MHz | Cb = 100 pF, 4.5V - 5.5V | 8 | |
| Bus capacitive loading | Cb | 400 | pF | 100 kHz mode | 8 | ||
| Bus capacitive loading | Cb | 100 | pF | 3.4 MHz mode | 8 | ||
| Clock high time (THIGH) | THIGH | 4000 | ns | 100 kHz mode, 2.7V-5.5V | 9 | ||
| Clock high time (THIGH) | THIGH | 600 | ns | 400 kHz mode, 2.7V-5.5V | 9 | ||
| Clock high time (THIGH) | THIGH | 120 | ns | 1.7 MHz mode, 4.5V-5.5V | 9 | ||
| Clock high time (THIGH) | THIGH | 60 | ns | 3.4 MHz mode, 4.5V-5.5V | 9 | ||
| Clock low time (TLOW) | TLOW | 4700 | ns | 100 kHz mode, 2.7V-5.5V | 9 | ||
| Clock low time (TLOW) | TLOW | 1300 | ns | 400 kHz mode, 2.7V-5.5V | 9 | ||
| Clock low time (TLOW) | TLOW | 320 | ns | 1.7 MHz mode, 4.5V-5.5V | 9 | ||
| Clock low time (TLOW) | TLOW | 160 | ns | 3.4 MHz mode, 4.5V-5.5V | 9 | ||
| Data input setup time (TSU:DAT) | TSU:DAT | 250 | ns | 100 kHz mode, Note 2 | 11 | ||
| Data input setup time (TSU:DAT) | TSU:DAT | 100 | ns | 400 kHz mode | 11 | ||
| Data input setup time (TSU:DAT) | TSU:DAT | 10 | ns | 1.7 MHz mode | 11 | ||
| High Voltage Command setup time (THVCSU) | THVCSU | 25 | uS | High Voltage Commands | 8 | ||
| High Voltage Command hold time (THVCHD) | THVCHD | 25 | uS | High Voltage Commands | 8 |
CAD (KiCad official)
- Symbol:
MCP4726A2T-E - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
mcp4726a2t-e-etched.step/mcp4726a2t-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4726a2t-e.step/mcp4726a2t-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (86 pp, sha256
f89f3345410b5013, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP4726A2T-E
**Microchip Tech** · Digital To Analog Converters (DAC) · SOT-23-6
MCP4726A2T-E from Microchip Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | Buffered analog DAC voltage output that swings from approximately 0V to approximately VDD, with a full-scale range of VSS to G × VREF and about 1Ω DC output impedance in Normal mode. |
| 2 | VSS | power_in | Ground reference pin for all circuitry on the device, which must be connected to a low-impedance ground plane. |
| 3 | VDD | power_in | Positive supply voltage input, relative to VSS, specified for 2.7V to 5.5V operation and recommended to be bypassed with about 0.1 µF ceramic plus 10 µF tantalum capacitors. |
| 4 | SDA | bidirectional | I2C serial data pin, an open-drain N-channel driver that requires a pull-up resistor from VDD and must only change state while SCL is low (except for Start and Stop conditions). |
| 5 | SCL | input | I2C serial clock input that accepts only external clocks from the master, with an open-drain N-channel driver that requires a pull-up resistor from VDD. |
| 6 | VREF | power_in | External voltage reference input that can be selected as the resistor ladder reference instead of VDD, optionally buffered, and limited to a maximum of VDD/2 when the output gain is 2. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOT-23-6 |
| Category | Data Acquisition |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VDD | 2.7 | | 5.5 | V | | 4 |
| Input Current | IDD | | 210 | 400 | µA | VREF1:VREF0 = 00, SCL = SDA = VSS, VOUT is unloaded, volatile DAC Register = 0x000 | 4 |
| Power-Down Current | IDDP | | 0.09 | 2 | µA | PD1:PD0 = 01 (Note 6), VOUT not connected | 4 |
| Power-Up Ramp Rate | VRAMP | 1 | | | V/S | Note 1, Note 4 | 4 |
| Offset Error | VOS | | 0.02 | 0.75 | % of FSR | Code = 0x000h, VREF1:VREF0 = 00, G = 0 | 4 |
| Zero-Scale Error | EZS | | 2.05 | 30.8 | LSb | MCP4726, Code = 0x000h | 4 |
| Full-Scale Error | EFS | | 4.1 | 82 | LSb | MCP4726, Code = 0xFFFh | 4 |
| Gain Error | gE | -2 | -0.1 | 2 | % of FSR | MCP4726, Code = 0xFFFh, VREF1:VREF0 = 00, G = 0; Note 2 | 4 |
| INL Error | INL | -14.5 | 2 | 14.5 | LSb | MCP4726 (codes: 100 to 4000); Note 7: VDD = VREF = 5.5V | 4 |
| DNL Error | DNL | -0.75 | 0.2 | 0.75 | LSb | MCP4726 (codes: 100 to 4000); Note 7: VDD = VREF = 5.5V | 4 |
| Short Circuit Current | ISC | 7 | 15 | 24 | mA | | 5 |
| External Reference Input Range (buffered mode) | VREF | 0.04 | | | V | Buffered mode | 5 |
| External Reference Input Range (unbuffered mode) | VREF | 0 | | | V | Unbuffered mode | 5 |
| Output Low Voltage | VOL | | | 0.4 | V | IOL = 3 mA | 6 |
| Input Leakage | ILI | -1 | | 1 | µA | SCL = SDA = VSS or SCL = SDA = VDD | 6 |
| Pin Capacitance | CPIN | | | 3 | pF | Note 5 | 6 |
| EEPROM Write Time | TWRITE | | 25 | 50 | ms | | 6 |
| Endurance | | 1 | | | Million Cycles | At +25°C, Note 1 | 6 |
| Voltage on VDD with respect to VSS | VDD | -0.6 | | 6.5 | V | | 3 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < 0, VI > VDD | 3 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < 0 or VO > VDD | 3 |
| Maximum input current source/sunk by SDA, SCL pins | | | | 2 | mA | | 3 |
| Maximum output current sunk by SDA Output pin | | | | 25 | mA | | 3 |
| Maximum current out of VSS pin | | | | 50 | mA | | 3 |
| Maximum current into VDD pin | | | | 50 | mA | | 3 |
| Maximum current sourced by the VOUT pin | | | | 40 | mA | | 3 |
| Maximum current sunk by the VOUT pin | | | | 40 | mA | | 3 |
| Maximum current sunk by the VREF pin | | | | 40 | µA | | 3 |
| Storage temperature | | -65 | | 150 | °C | | 3 |
| Ambient temperature with power applied | | -55 | | 125 | °C | | 3 |
| ESD protection on all pins (HBM) | | 6 | | | kV | HBM | 3 |
| ESD protection on all pins (MM) | | 400 | | | V | MM | 3 |
| Maximum Junction Temperature | TJ | | | 150 | °C | | 3 |
| Specified Temperature Range | TA | -40 | | 125 | °C | | 13 |
| Operating Temperature Range | TA | -40 | | 125 | °C | Note 1 | 13 |
| Thermal Resistance, 6L-SOT-23 | θJA | | 190 | | °C/W | | 13 |
| SCL pin Frequency (Standard mode) | FSCL | 0 | | 100 | kHz | Cb = 400 pF, 2.7V - 5.5V | 8 |
| SCL pin Frequency (Fast mode) | FSCL | 0 | | 400 | kHz | Cb = 400 pF, 2.7V - 5.5V | 8 |
| SCL pin Frequency (High-Speed 1.7 MHz) | FSCL | 0 | | 1.7 | MHz | Cb = 400 pF, 4.5V - 5.5V | 8 |
| SCL pin Frequency (High-Speed 3.4 MHz) | FSCL | 0 | | 3.4 | MHz | Cb = 100 pF, 4.5V - 5.5V | 8 |
| Bus capacitive loading | Cb | | | 400 | pF | 100 kHz mode | 8 |
| Bus capacitive loading | Cb | | | 100 | pF | 3.4 MHz mode | 8 |
| Clock high time (THIGH) | THIGH | 4000 | | | ns | 100 kHz mode, 2.7V-5.5V | 9 |
| Clock high time (THIGH) | THIGH | 600 | | | ns | 400 kHz mode, 2.7V-5.5V | 9 |
| Clock high time (THIGH) | THIGH | 120 | | | ns | 1.7 MHz mode, 4.5V-5.5V | 9 |
| Clock high time (THIGH) | THIGH | 60 | | | ns | 3.4 MHz mode, 4.5V-5.5V | 9 |
| Clock low time (TLOW) | TLOW | 4700 | | | ns | 100 kHz mode, 2.7V-5.5V | 9 |
| Clock low time (TLOW) | TLOW | 1300 | | | ns | 400 kHz mode, 2.7V-5.5V | 9 |
| Clock low time (TLOW) | TLOW | 320 | | | ns | 1.7 MHz mode, 4.5V-5.5V | 9 |
| Clock low time (TLOW) | TLOW | 160 | | | ns | 3.4 MHz mode, 4.5V-5.5V | 9 |
| Data input setup time (TSU:DAT) | TSU:DAT | 250 | | | ns | 100 kHz mode, Note 2 | 11 |
| Data input setup time (TSU:DAT) | TSU:DAT | 100 | | | ns | 400 kHz mode | 11 |
| Data input setup time (TSU:DAT) | TSU:DAT | 10 | | | ns | 1.7 MHz mode | 11 |
| High Voltage Command setup time (THVCSU) | THVCSU | 25 | | | uS | High Voltage Commands | 8 |
| High Voltage Command hold time (THVCHD) | THVCHD | 25 | | | uS | High Voltage Commands | 8 |
## CAD (KiCad official)
- Symbol: `MCP4726A2T-E`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `mcp4726a2t-e-etched.step` / `mcp4726a2t-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp4726a2t-e.step` / `mcp4726a2t-e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589795360673083392) (86 pp, sha256 `f89f3345410b5013`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp4726a2t-e-datasheet.pdf)