component
MCP4716A2T-E
Public Made by Adomby adom
Microchip Tech Digital To Analog Converters (DAC), SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownMCP4716A2T-E
Microchip Tech · Digital To Analog Converters (DAC) · SOT-23-6
MCP4716A2T-E from Microchip Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | Buffered DAC analog output that swings from approximately 0 V to approximately VDD, with about 1 Ω DC output impedance in Normal mode and a selectable 1 kΩ, 125 kΩ or 640 kΩ pull-down in Power-Down mode. |
| 2 | VSS | power_in | Device ground reference for all circuitry, which must be connected to a ground plane through a low-impedance connection. |
| 3 | VDD | power_in | Positive supply input referenced to VSS, specified for 2.7 V to 5.5 V single-supply operation and recommended to be bypassed with about 0.1 µF ceramic plus 10 µF tantalum. |
| 4 | SDA | bidirectional | I2C serial data pin, an open-drain N-channel driver that requires a pull-up resistor to VDD and must be stable while SCL is high except during Start and Stop conditions. |
| 5 | SCL | input | I2C serial clock pin that accepts only external clocks from the master, uses an open-drain N-channel driver requiring a pull-up resistor to VDD, and is recommended with 5 kΩ to 10 kΩ pull-ups for 100 kHz to 400 kHz operation. |
| 6 | VREF | power_in | External voltage reference input used when the VREF pin is selected as the resistor ladder reference, where the gain-of-2 option limits the VREF voltage to a maximum of VDD/2 and the pin is disconnected internally when VDD is selected as reference. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOT-23-6 |
| Category | Data Acquisition |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage (VDD) | VDD | 2.7 | 5.5 | V | 4 | ||
| Input Current (IDD) | IDD | 210 | 400 | µA | VREF1:VREF0 = 00, SCL = SDA = VSS, VOUT unloaded, volatile DAC register = 0x000 | 4 | |
| Power-Down Current | IDDP | 0.09 | 2 | µA | PD1:PD0 = 01 (Note 6), VOUT not connected | 4 | |
| Power-Up Ramp Rate | VRAMP | 1 | V/S | Note 1, Note 4 | 4 | ||
| Offset Error | VOS | 0.02 | 0.75 | % of FSR | Code = 0x000h, VREF1:VREF0 = 00, G = 0 | 4 | |
| Zero-Scale Error (MCP4716) | EZS | 0.52 | 7.7 | LSb | MCP4716, Code = 0x000h | 4 | |
| Full-Scale Error (MCP4716) | EFS | 1.1 | 20.5 | LSb | MCP4716, Code = 0x3FFh | 4 | |
| Gain Error (MCP4716) | gE | -2 | -0.1 | 2 | % of FSR | MCP4716, Code = 0x3FFh, VREF1:VREF0 = 00, G = 0 | 4 |
| INL Error (MCP4716) | INL | -3.625 | 0.5 | 3.625 | LSb | MCP4716 (codes: 25 to 1000) | 4 |
| DNL Error (MCP4716) | DNL | -0.188 | 0.05 | 0.188 | LSb | MCP4716 (codes: 25 to 1000) | 4 |
| Short Circuit Current | ISC | 7 | 15 | 24 | mA | 5 | |
| External Reference Input Range (buffered mode, lower limit) | VREF | 0.04 | V | Buffered mode | 5 | ||
| External Reference Input Range (unbuffered mode, lower limit) | VREF | 0 | V | Unbuffered mode | 5 | ||
| Output Low Voltage | VOL | 0.4 | V | IOL = 3 mA | 6 | ||
| Input Leakage | ILI | -1 | 1 | µA | SCL = SDA = VSS or SCL = SDA = VDD | 6 | |
| Pin Capacitance | CPIN | 3 | pF | (Note 5) | 6 | ||
| EEPROM Write Time | TWRITE | 25 | 50 | ms | 6 | ||
| Endurance | 1 | Million Cycles | At +25°C, (Note 1) | 6 | |||
| Voltage on VDD with respect to VSS | -0.6 | 6.5 | V | 3 | |||
| Voltage on all pins with respect to VSS (lower limit) | -0.3 | V | 3 | ||||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0, VI > VDD | 3 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VDD | 3 | |
| Maximum input current source/sunk by SDA, SCL pins | 2 | mA | 3 | ||||
| Maximum output current sunk by SDA output pin | 25 | mA | 3 | ||||
| Maximum current out of VSS pin | 50 | mA | 3 | ||||
| Maximum current into VDD pin | 50 | mA | 3 | ||||
| Maximum current sourced by VOUT pin | 40 | mA | 3 | ||||
| Maximum current sunk by VOUT pin | 40 | mA | 3 | ||||
| Maximum current sunk by VREF pin | 40 | µA | 3 | ||||
| ESD protection, HBM | 6 | kV | HBM | 3 | |||
| ESD protection, MM | 400 | V | MM | 3 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 3 | |||
| Ambient temperature with power applied | -55 | 125 | °C | 3 | |||
| Storage temperature (absolute maximum) | -65 | 150 | °C | 3 | |||
| Specified Temperature Range | TA | -40 | 125 | °C | 13 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | Note 1 | 13 | |
| Storage Temperature Range | TA | -65 | 150 | °C | 13 | ||
| SCL pin frequency, Standard mode | FSCL | 0 | 100 | kHz | Cb = 400 pF, 2.7V - 5.5V | 8 | |
| SCL pin frequency, Fast mode | FSCL | 0 | 400 | kHz | Cb = 400 pF, 2.7V - 5.5V | 8 | |
| SCL pin frequency, High-Speed 1.7 MHz | FSCL | 0 | 1.7 | MHz | Cb = 400 pF, 4.5V - 5.5V | 8 | |
| SCL pin frequency, High-Speed 3.4 MHz | FSCL | 0 | 3.4 | MHz | Cb = 100 pF, 4.5V - 5.5V | 8 | |
| Data input setup time, 100 kHz mode | TSU:DAT | 250 | ns | Note 2 | 11 | ||
| Data input setup time, 400 kHz mode | TSU:DAT | 100 | ns | 400 kHz mode | 11 | ||
| Data input setup time, 1.7 MHz mode | TSU:DAT | 10 | ns | 1.7 MHz mode | 11 | ||
| Data input setup time, 3.4 MHz mode | TSU:DAT | 10 | ns | 3.4 MHz mode | 11 | ||
| Output valid from clock, 100 kHz mode | TAA | 3750 | ns | Note 1, Note 8 | 11 | ||
| Output valid from clock, 400 kHz mode | TAA | 1200 | ns | 400 kHz mode | 11 | ||
| Output valid from clock, 1.7 MHz mode | TAA | 150 | ns | Cb = 100 pF, Note 1, Note 7, Note 8 | 11 | ||
| Output valid from clock, 1.7 MHz mode | TAA | 310 | ns | Cb = 400 pF, Note 1, Note 5, Note 8 | 11 | ||
| Output valid from clock, 3.4 MHz mode | TAA | 150 | ns | Cb = 100 pF, Note 1, Note 8 | 11 | ||
| Thermal Resistance, 6L-SOT-23 | θJA | 190 | °C/W | 13 |
CAD (KiCad official)
- Symbol:
MCP4716A2T-E - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
mcp4716a2t-e-etched.step/mcp4716a2t-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4716a2t-e.step/mcp4716a2t-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (86 pp, sha256
f89f3345410b5013, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).