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MCP4706A0T-E

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Microchip Tech Digital To Analog Converters (DAC), SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MCP4706A0T-E

Microchip Tech · Digital To Analog Converters (DAC) · SOT-23-6

MCP4706A0T-E from Microchip Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT output DAC buffered analog output that swings from approximately 0V to approximately VDD, with full-scale range from VSS to G × VRL (G = 1x or 2x gain).
2 VSS power_in Device ground reference that must be connected to a ground plane through a low-impedance connection.
3 VDD power_in Positive supply voltage input relative to VSS, with a ~0.1 µF ceramic bypass capacitor recommended close to the pin.
4 SDA bidirectional I2C serial data pin, an open-drain N-channel driver that requires a pull-up resistor from VDD; data must remain stable while SCL is high except during Start and Stop conditions.
5 SCL input I2C serial clock pin that accepts only external clocks from the master, with an open-drain N-channel driver requiring a pull-up resistor from VDD.
6 VREF power_in External voltage reference input that can be selected as the resistor ladder reference (buffered or unbuffered), and is disconnected from the internal circuit when VDD is selected as the reference.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOT-23-6
Category Data Acquisition
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage on VDD with respect to VSS VDD -0.6 6.5 V 3
Voltage on all pins with respect to VSS -0.3 V 3
Input clamp current IIK -20 20 mA VI < 0, VI > VDD 3
Output clamp current IOK -20 20 mA VO < 0 or VO > VDD 3
Maximum input current source/sunk by SDA, SCL pins 2 mA 3
Maximum output current sunk by SDA output pin 25 mA 3
Maximum current out of VSS pin 50 mA 3
Maximum current into VDD pin 50 mA 3
Maximum current sourced by the VOUT pin 40 mA 3
Maximum current sunk by the VOUT pin 40 mA 3
Maximum current sunk by the VREF pin 40 µA 3
Storage temperature -65 150 °C 3
Ambient temperature with power applied -55 125 °C 3
ESD protection on all pins (HBM) 6 kV 3
ESD protection on all pins (MM) 400 V 3
Maximum Junction Temperature (TJ) TJ 150 °C 3
Input Voltage VDD 2.7 5.5 V 4
Input Current IDD 210 400 µA VREF1:VREF0 = 00, SCL = SDA = VSS, VOUT is unloaded, volatile DAC Register = 0x000 4
Power-Down Current IDDP 0.09 2 µA PD1:PD0 = 01 (Note 6), VOUT not connected 4
Power-Up Ramp Rate VRAMP 1 V/S (Note 1, Note 4) 4
Offset Error VOS 0.75 % of FSR Code = 0x000h, VREF1:VREF0 = 00, G = 0 4
Zero-Scale Error EZS 0.13 2 LSb MCP4706, Code = 0x00h 4
Full-Scale Error EFS 0.3 5.2 LSb MCP4706, Code = 0xFFh 4
Gain Error gE -2 -0.1 2 % of FSR MCP4706, Code = 0xFFh, VREF1:VREF0 = 00, G = 0 4
INL Error INL -0.907 0.907 LSb MCP4706 (codes: 6 to 250) 4
DNL Error DNL -0.05 0.05 LSb MCP4706 (codes: 6 to 250) 4
Short Circuit Current ISC 7 15 24 mA 5
External Reference (VREF) Input Range, buffered mode VREF 0.04 V Buffered mode 5
External Reference (VREF) Input Range, unbuffered mode VREF 0 V Unbuffered mode 5
Output Low Voltage VOL 0.4 V IOL = 3 mA 6
Input Leakage ILI -1 1 µA SCL = SDA = VSS or SCL = SDA = VDD 6
Pin Capacitance CPIN 3 pF (Note 5) 6
EEPROM Write Time TWRITE 25 50 ms 6
Endurance 1 Million Cycles At +25°C, (Note 1) 6
SCL pin Frequency, Standard mode FSCL 0 100 kHz Cb = 400 pF, 2.7V - 5.5V 8
SCL pin Frequency, Fast mode FSCL 0 400 kHz Cb = 400 pF, 2.7V - 5.5V 8
SCL pin Frequency, High-Speed 3.4 MHz mode FSCL 0 3.4 MHz Cb = 100 pF, 4.5V - 5.5V 8
Start condition setup time, 100 kHz mode TSU:STA 4700 ns Only relevant for repeated Start condition 8
Start condition hold time, 100 kHz mode THD:STA 4000 ns After this period, the first clock pulse is generated 8
Stop condition setup time, 100 kHz mode TSU:STO 4000 ns 8
Stop condition hold time, 100 kHz mode THD:STO 4000 ns 8
Clock high time, 100 kHz mode THIGH 4000 ns 2.7V-5.5V 9
Clock low time, 100 kHz mode TLOW 4700 ns 2.7V-5.5V 9
Data input setup time, 100 kHz mode TSU:DAT 250 ns Note 2 11
Output valid from clock, 100 kHz mode TAA 3750 ns Note 1, Note 8 11
Bus free time, 100 kHz mode TBUF 4700 ns Time the bus must be free before a new transmission can start 11
Input filter spike suppression (SDA and SCL), 100 kHz mode TSP 50 ns 12
Output valid from clock, 400 kHz mode TAA 1200 ns 11
Data input setup time, 400 kHz mode TSU:DAT 100 ns 11
Clock high time, 400 kHz mode THIGH 600 ns 2.7V-5.5V 9
Clock low time, 400 kHz mode TLOW 1300 ns 2.7V-5.5V 9
Output valid from clock, 3.4 MHz mode TAA 150 ns Cb = 100 pF, Note 1, Note 8 11
Clock high time, 3.4 MHz mode THIGH 60 ns 4.5V-5.5V 9
Clock low time, 3.4 MHz mode TLOW 160 ns 4.5V-5.5V 9
Bus capacitive loading, 3.4 MHz mode D102 Cb 100 pF 8
Specified Temperature Range TA -40 125 °C 13
Operating Temperature Range TA -40 125 °C Note 1 13
Thermal Resistance, 6L-SOT-23 θJA 190 °C/W 13

CAD (KiCad official)

  • Symbol: MCP4706A0T-E
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: mcp4706a0t-e-etched.step / mcp4706a0t-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp4706a0t-e.step / mcp4706a0t-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (86 pp, sha256 f89f3345410b5013, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF