component
MCP4662-502E
Public Made by Adomby adom
Microchip Tech Digital Potentiometers, MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MCP4662-502E
Microchip Tech · Digital Potentiometers · MSOP-10
MCP4662-502E from Microchip Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HVC/A0 | input | High Voltage Command / Address 0 input; A0 address bit is latched at POR/BOR, and the voltage on the pin selects normal or High Voltage command (HVC/A0 = VIHH); high-voltage tolerant (up to 12.5V) with Schmitt trigger and smart pull-up. |
| 2 | SCL | input | I2C serial clock input from the host controller; the device is a slave so it accepts only external clock signals; high-voltage tolerant with Schmitt trigger. |
| 3 | SDA | bidirectional | I2C serial data I/O with an open-drain N-channel driver, connected to the host controller SDA; high-voltage tolerant with Schmitt trigger. |
| 4 | VSS | power_in | Device ground reference. |
| 5 | P1B | passive | Potentiometer 1 terminal B, the fixed zero-scale connection (wiper value 0x00); no polarity, voltage must be between VSS and VDD. |
| 6 | P1W | passive | Potentiometer 1 wiper terminal; no polarity, voltage must be between VSS and VDD. |
| 7 | P0W | passive | Potentiometer 0 wiper terminal; no polarity, voltage must be between VSS and VDD. |
| 8 | P0B | passive | Potentiometer 0 terminal B, the fixed zero-scale connection (wiper value 0x00); no polarity, voltage must be between VSS and VDD. |
| 9 | A1 | input | I2C Address 1 input which, with A2 and A0, allows up to eight devices on one I2C bus; high-voltage tolerant with Schmitt trigger and smart pull-up. |
| 10 | VDD | power_in | Positive power supply input relative to VSS; electrical performance may not meet specifications below 2.7V (device operation 1.8V to 5.5V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | MSOP-10 |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal Resistance (-502) | RAB | 4 | 5 | 6 | kΩ | -502 devices (Note 1), ±20% | 5 |
| Supply Voltage | VDD | 2.7 | 5.5 | V | 4 | ||
| Supply Voltage (serial interface only) | VDD | 1.8 | 2.7 | V | Serial Interface only. | 4 | |
| VDD Start Voltage to ensure Wiper Reset | VBOR | 1.65 | V | RAM retention voltage (VRAM) < VBOR | 4 | ||
| Delay after device exits reset state | TBORD | 10 | 20 | µs | VDD > VBOR | 4 | |
| Supply Current, 3.4 MHz | IDD | 600 | µA | Serial Interface Active, HVC/A0 = VIH (or VIL), Write all 0's to Volatile Wiper 0, VDD = 5.5V, FSCL = 3.4 MHz | 4 | ||
| Supply Current, 100 kHz | IDD | 250 | µA | Serial Interface Active, HVC/A0 = VIH (or VIL), Write all 0's to Volatile Wiper 0, VDD = 5.5V, FSCL = 100 kHz | 4 | ||
| Supply Current, interface inactive | IDD | 2.5 | 5 | µA | Serial Interface Inactive (Stop condition, SCL = SDA = VIH), Wiper = 0, VDD = 5.5V, HVC/A0 = VIH | 4 | |
| HVC pin voltage range (VDD ≥ 4.5V) | VHV | 12.5 | V | VDD ≥ 4.5V; min is VSS | 4 | ||
| Wiper Resistance | RW | 75 | 160 | Ω | VDD = 5.5 V, IW = 2.0 mA, code = 00h | 5 | |
| Wiper Resistance | RW | 75 | 300 | Ω | VDD = 2.7 V, IW = 2.0 mA, code = 00h | 5 | |
| Nominal Resistance Match (MCP46X2) | /RBW0-RBW1//RBW | 0.25 | 1.5 | % | MCP46X2 devices only, Code = Full-Scale | 5 | |
| Nominal Resistance Tempco | ΔRAB/ΔT | 50 | ppm/°C | TA = -20°C to +70°C | 5 | ||
| Nominal Resistance Tempco | ΔRAB/ΔT | 100 | ppm/°C | TA = -40°C to +85°C | 5 | ||
| Nominal Resistance Tempco | ΔRAB/ΔT | 150 | ppm/°C | TA = -40°C to +125°C | 5 | ||
| Ratiometric Tempco | ΔVWB/ΔT | 15 | ppm/°C | Code = Midscale (80h or 40h) | 5 | ||
| Resistor Terminal Input Voltage Range | VA,VW,VB | 0 | 5.5 | V | Vss to VDD, Note 5, Note 6 | 5 | |
| Max current through terminal W | IT | 2.5 | mA | Terminal W IAW or IBW, W = FS or ZS | 6 | ||
| Max current through terminal B | IT | 2.5 | mA | Terminal B IBW, W = Zero Scale (ZS) | 6 | ||
| Max current A and B, 5k | IAB | 1.38 | mA | VB = 0V, VA = 5.5V, RAB(MIN) = 4000 | 6 | ||
| Leakage current into W or B | IWL | 100 | nA | MCP4XX2 PxB = PxW = VSS | 6 | ||
| Leakage current, terminals disconnected | IWL | 100 | nA | Terminals Disconnected (R1HW = R0HW = 0) | 6 | ||
| Rheostat INL 5k 8-bit | R-INL | -1.5 | 0.5 | 1.5 | LSb | 5 k 8-bit 5.5V, IW = 900 µA, MCP4XX2 | 9 |
| Rheostat INL 5k 8-bit | R-INL | -8.25 | 4.5 | 8.25 | LSb | 3.0V, IW = 480 µA (Note 7) | 9 |
| Rheostat DNL 5k 8-bit | R-DNL | -0.5 | 0.25 | 0.5 | LSb | 5 k 8-bit 5.5V, IW = 900 µA, MCP4XX2 | 10 |
| Rheostat DNL 5k 8-bit | R-DNL | -1 | 0.5 | 1 | LSb | 3.0V, IW = 480 µA (Note 7) | 10 |
| Bandwidth -3 dB 5k 8-bit | BW | 2 | MHz | 5 k 8-bit Code = 80h, load = 30 pF | 8 | ||
| Capacitance (PA) | CAW | 75 | pF | f =1 MHz, Code = Full-Scale | 10 | ||
| Capacitance (PW) | CW | 120 | pF | f =1 MHz, Code = Full-Scale | 10 | ||
| Capacitance (PB) | CBW | 75 | pF | f =1 MHz, Code = Full-Scale | 10 | ||
| Schmitt Trigger High Input Threshold (except SDA/SCL) | VIH | 0.45 | V | 2.7V ≤ VDD ≤ 5.5V; min is 0.45 VDD | 11 | ||
| Schmitt Trigger High Input Threshold SDA/SCL | VIH | 0.7 | 12.5 | V | min 0.7 VDD, max VMAX, 100 kHz to 3.4 MHz | 11 | |
| Schmitt Trigger Low Input Threshold (except SDA/SCL) | VIL | 0.2 | V | max is 0.2VDD, all inputs except SDA and SCL | 11 | ||
| Schmitt Trigger Low Input Threshold SDA/SCL | VIL | -0.5 | 0.3 | V | max is 0.3VDD, 100 kHz to 3.4 MHz | 11 | |
| High Voltage Limit | VMAX | 12.5 | V | Pin can tolerate VMAX or less. | 11 | ||
| Output Low Voltage (SDA) | VOL | 0 | 0.4 | V | VDD ≥ 2.0V, IOL = 3 mA | 12 | |
| Output Low Voltage (SDA) | VOL | 0 | 0.2 | V | VDD < 2.0V, IOL = 1 mA; max is 0.2VDD | 12 | |
| Weak Pull-up/Pull-down Current | IPU | 1.75 | mA | Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VIHH = 12.5V | 12 | ||
| Input Leakage Current | IIL | -1 | 1 | µA | VIN = VDD and VIN = VSS | 12 | |
| Pin Capacitance | CIN, COUT | 10 | pF | fC = 3.4 MHz | 12 | ||
| Power Supply Sensitivity 8-bit | PSS | 0.0015 | 0.0035 | %/% | VDD = 2.7V to 5.5V, VA = 2.7V, Code = 80h | 12 | |
| SCL clock frequency, Standard Mode | FSCL | 0 | 100 | kHz | Cb = 400 pF, 1.8V - 5.5V | 13 | |
| SCL clock frequency, Fast Mode | FSCL | 0 | 400 | kHz | Cb = 400 pF, 2.7V - 5.5V | 13 | |
| SCL clock frequency, High-Speed 3.4 | FSCL | 0 | 3.4 | MHz | Cb = 100 pF, 4.5V - 5.5V | 13 | |
| Clock high time, 100 kHz | THIGH | 4000 | ns | 1.8V-5.5V | 14 | ||
| Clock low time, 100 kHz | TLOW | 4700 | ns | 1.8V-5.5V | 14 | ||
| Voltage on VDD with respect to VSS | VDD | -0.6 | 7 | V | 3 | ||
| Voltage on HVC/A0, A1, A2, SCL, SDA | -0.6 | 12.5 | V | with respect to VSS | 3 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0, VI > VDD, VI > VPP on HV pins | 3 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VDD | 3 | |
| Max current into PXA, PXW & PXB pins | -2.5 | 2.5 | mA | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Ambient temperature with power applied | TA | -40 | 125 | °C | 3 | ||
| Maximum Junction Temperature | TJ | 150 | °C | 3 | |||
| Thermal Resistance, 10L-MSOP | θJA | 202 | °C/W | 16 |
CAD (KiCad official)
- Symbol:
MCP4662-502E - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
mcp4662-502e-etched.step/mcp4662-502e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4662-502e.step/mcp4662-502e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (102 pp, sha256
ee77464c39584a73, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP4662-502E
**Microchip Tech** · Digital Potentiometers · MSOP-10
MCP4662-502E from Microchip Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HVC/A0 | input | High Voltage Command / Address 0 input; A0 address bit is latched at POR/BOR, and the voltage on the pin selects normal or High Voltage command (HVC/A0 = VIHH); high-voltage tolerant (up to 12.5V) with Schmitt trigger and smart pull-up. |
| 2 | SCL | input | I2C serial clock input from the host controller; the device is a slave so it accepts only external clock signals; high-voltage tolerant with Schmitt trigger. |
| 3 | SDA | bidirectional | I2C serial data I/O with an open-drain N-channel driver, connected to the host controller SDA; high-voltage tolerant with Schmitt trigger. |
| 4 | VSS | power_in | Device ground reference. |
| 5 | P1B | passive | Potentiometer 1 terminal B, the fixed zero-scale connection (wiper value 0x00); no polarity, voltage must be between VSS and VDD. |
| 6 | P1W | passive | Potentiometer 1 wiper terminal; no polarity, voltage must be between VSS and VDD. |
| 7 | P0W | passive | Potentiometer 0 wiper terminal; no polarity, voltage must be between VSS and VDD. |
| 8 | P0B | passive | Potentiometer 0 terminal B, the fixed zero-scale connection (wiper value 0x00); no polarity, voltage must be between VSS and VDD. |
| 9 | A1 | input | I2C Address 1 input which, with A2 and A0, allows up to eight devices on one I2C bus; high-voltage tolerant with Schmitt trigger and smart pull-up. |
| 10 | VDD | power_in | Positive power supply input relative to VSS; electrical performance may not meet specifications below 2.7V (device operation 1.8V to 5.5V). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | MSOP-10 |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal Resistance (-502) | RAB | 4 | 5 | 6 | kΩ | -502 devices (Note 1), ±20% | 5 |
| Supply Voltage | VDD | 2.7 | | 5.5 | V | | 4 |
| Supply Voltage (serial interface only) | VDD | 1.8 | | 2.7 | V | Serial Interface only. | 4 |
| VDD Start Voltage to ensure Wiper Reset | VBOR | | | 1.65 | V | RAM retention voltage (VRAM) < VBOR | 4 |
| Delay after device exits reset state | TBORD | | 10 | 20 | µs | VDD > VBOR | 4 |
| Supply Current, 3.4 MHz | IDD | | | 600 | µA | Serial Interface Active, HVC/A0 = VIH (or VIL), Write all 0's to Volatile Wiper 0, VDD = 5.5V, FSCL = 3.4 MHz | 4 |
| Supply Current, 100 kHz | IDD | | | 250 | µA | Serial Interface Active, HVC/A0 = VIH (or VIL), Write all 0's to Volatile Wiper 0, VDD = 5.5V, FSCL = 100 kHz | 4 |
| Supply Current, interface inactive | IDD | | 2.5 | 5 | µA | Serial Interface Inactive (Stop condition, SCL = SDA = VIH), Wiper = 0, VDD = 5.5V, HVC/A0 = VIH | 4 |
| HVC pin voltage range (VDD ≥ 4.5V) | VHV | | | 12.5 | V | VDD ≥ 4.5V; min is VSS | 4 |
| Wiper Resistance | RW | | 75 | 160 | Ω | VDD = 5.5 V, IW = 2.0 mA, code = 00h | 5 |
| Wiper Resistance | RW | | 75 | 300 | Ω | VDD = 2.7 V, IW = 2.0 mA, code = 00h | 5 |
| Nominal Resistance Match (MCP46X2) | /RBW0-RBW1//RBW | | 0.25 | 1.5 | % | MCP46X2 devices only, Code = Full-Scale | 5 |
| Nominal Resistance Tempco | ΔRAB/ΔT | | 50 | | ppm/°C | TA = -20°C to +70°C | 5 |
| Nominal Resistance Tempco | ΔRAB/ΔT | | 100 | | ppm/°C | TA = -40°C to +85°C | 5 |
| Nominal Resistance Tempco | ΔRAB/ΔT | | 150 | | ppm/°C | TA = -40°C to +125°C | 5 |
| Ratiometric Tempco | ΔVWB/ΔT | | 15 | | ppm/°C | Code = Midscale (80h or 40h) | 5 |
| Resistor Terminal Input Voltage Range | VA,VW,VB | 0 | | 5.5 | V | Vss to VDD, Note 5, Note 6 | 5 |
| Max current through terminal W | IT | | | 2.5 | mA | Terminal W IAW or IBW, W = FS or ZS | 6 |
| Max current through terminal B | IT | | | 2.5 | mA | Terminal B IBW, W = Zero Scale (ZS) | 6 |
| Max current A and B, 5k | IAB | | | 1.38 | mA | VB = 0V, VA = 5.5V, RAB(MIN) = 4000 | 6 |
| Leakage current into W or B | IWL | | 100 | | nA | MCP4XX2 PxB = PxW = VSS | 6 |
| Leakage current, terminals disconnected | IWL | | 100 | | nA | Terminals Disconnected (R1HW = R0HW = 0) | 6 |
| Rheostat INL 5k 8-bit | R-INL | -1.5 | 0.5 | 1.5 | LSb | 5 k 8-bit 5.5V, IW = 900 µA, MCP4XX2 | 9 |
| Rheostat INL 5k 8-bit | R-INL | -8.25 | 4.5 | 8.25 | LSb | 3.0V, IW = 480 µA (Note 7) | 9 |
| Rheostat DNL 5k 8-bit | R-DNL | -0.5 | 0.25 | 0.5 | LSb | 5 k 8-bit 5.5V, IW = 900 µA, MCP4XX2 | 10 |
| Rheostat DNL 5k 8-bit | R-DNL | -1 | 0.5 | 1 | LSb | 3.0V, IW = 480 µA (Note 7) | 10 |
| Bandwidth -3 dB 5k 8-bit | BW | | 2 | | MHz | 5 k 8-bit Code = 80h, load = 30 pF | 8 |
| Capacitance (PA) | CAW | | 75 | | pF | f =1 MHz, Code = Full-Scale | 10 |
| Capacitance (PW) | CW | | 120 | | pF | f =1 MHz, Code = Full-Scale | 10 |
| Capacitance (PB) | CBW | | 75 | | pF | f =1 MHz, Code = Full-Scale | 10 |
| Schmitt Trigger High Input Threshold (except SDA/SCL) | VIH | 0.45 | | | V | 2.7V ≤ VDD ≤ 5.5V; min is 0.45 VDD | 11 |
| Schmitt Trigger High Input Threshold SDA/SCL | VIH | 0.7 | | 12.5 | V | min 0.7 VDD, max VMAX, 100 kHz to 3.4 MHz | 11 |
| Schmitt Trigger Low Input Threshold (except SDA/SCL) | VIL | | | 0.2 | V | max is 0.2VDD, all inputs except SDA and SCL | 11 |
| Schmitt Trigger Low Input Threshold SDA/SCL | VIL | -0.5 | | 0.3 | V | max is 0.3VDD, 100 kHz to 3.4 MHz | 11 |
| High Voltage Limit | VMAX | | | 12.5 | V | Pin can tolerate VMAX or less. | 11 |
| Output Low Voltage (SDA) | VOL | 0 | | 0.4 | V | VDD ≥ 2.0V, IOL = 3 mA | 12 |
| Output Low Voltage (SDA) | VOL | 0 | | 0.2 | V | VDD < 2.0V, IOL = 1 mA; max is 0.2VDD | 12 |
| Weak Pull-up/Pull-down Current | IPU | | | 1.75 | mA | Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VIHH = 12.5V | 12 |
| Input Leakage Current | IIL | -1 | | 1 | µA | VIN = VDD and VIN = VSS | 12 |
| Pin Capacitance | CIN, COUT | | 10 | | pF | fC = 3.4 MHz | 12 |
| Power Supply Sensitivity 8-bit | PSS | | 0.0015 | 0.0035 | %/% | VDD = 2.7V to 5.5V, VA = 2.7V, Code = 80h | 12 |
| SCL clock frequency, Standard Mode | FSCL | 0 | | 100 | kHz | Cb = 400 pF, 1.8V - 5.5V | 13 |
| SCL clock frequency, Fast Mode | FSCL | 0 | | 400 | kHz | Cb = 400 pF, 2.7V - 5.5V | 13 |
| SCL clock frequency, High-Speed 3.4 | FSCL | 0 | | 3.4 | MHz | Cb = 100 pF, 4.5V - 5.5V | 13 |
| Clock high time, 100 kHz | THIGH | 4000 | | | ns | 1.8V-5.5V | 14 |
| Clock low time, 100 kHz | TLOW | 4700 | | | ns | 1.8V-5.5V | 14 |
| Voltage on VDD with respect to VSS | VDD | -0.6 | | 7 | V | | 3 |
| Voltage on HVC/A0, A1, A2, SCL, SDA | | -0.6 | | 12.5 | V | with respect to VSS | 3 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < 0, VI > VDD, VI > VPP on HV pins | 3 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < 0 or VO > VDD | 3 |
| Max current into PXA, PXW & PXB pins | | -2.5 | | 2.5 | mA | | 3 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| Ambient temperature with power applied | TA | -40 | | 125 | °C | | 3 |
| Maximum Junction Temperature | TJ | | | 150 | °C | | 3 |
| Thermal Resistance, 10L-MSOP | θJA | | 202 | | °C/W | | 16 |
## CAD (KiCad official)
- Symbol: `MCP4662-502E`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files: `mcp4662-502e-etched.step` / `mcp4662-502e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp4662-502e.step` / `mcp4662-502e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/mcp4662-502e-datasheet.pdf) (102 pp, sha256 `ee77464c39584a73`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp4662-502e-datasheet.pdf)