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MCP4652T-104E

Microchip Tech · Digital Potentiometers · DFN-10-EP(3x3)

MCP4652T-104E from Microchip Tech, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 HVC/A0 input High Voltage Command / Address 0 input; A0 is latched at POR/BOR, and a voltage of VIHH on the pin makes the I2C command a High Voltage command.
2 SCL input I2C serial clock input from the host; the device is a slave and accepts only external clock signals, with high-voltage-tolerant Schmitt-trigger input.
3 SDA bidirectional I2C serial data I/O with an open-drain N-channel driver, high-voltage-tolerant Schmitt-trigger input.
4 VSS power_in Ground reference for the device.
5 P1B passive Potentiometer 1 (rheostat) terminal B, the zero-scale connection (wiper value 0x00); no polarity, voltage must be between VSS and VDD.
6 P1W passive Potentiometer 1 wiper terminal; no polarity, voltage must be between VSS and VDD.
7 P0W passive Potentiometer 0 wiper terminal; no polarity, voltage must be between VSS and VDD.
8 P0B passive Potentiometer 0 (rheostat) terminal B, the zero-scale connection (wiper value 0x00); no polarity, voltage must be between VSS and VDD.
9 A1 input I2C Address 1 input; with A2 and A0 allows up to eight devices on one I2C bus; high-voltage-tolerant Schmitt-trigger input.
10 VDD power_in Positive power supply input relative to VSS; 1.8V to 5.5V device operation, 2.7V to 5.5V for specified characteristics.
11 EP passive Exposed thermal pad connected to the die substrate; tie to the same potential as VSS or leave unconnected.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package DFN-10-EP(3x3)
Category ADC/DAC/Data Conversion
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Nominal resistance (-104 device) RAB 80 100 120 kΩ -104 devices (Note 1), resistance between terminal A and B 5
Resistance tolerance RAB -20 20 % Resistance (± 20%) 5
Supply voltage VDD 2.7 5.5 V 4
Supply voltage, serial interface only VDD 1.8 2.7 V Serial Interface only 4
Operating temperature TA -40 125 °C Extended 16
HVC pin voltage range VHV 0 12.5 V VDD ≥ 4.5V; min printed as VSS 4
VDD start voltage to ensure wiper reset VBOR 1.65 V RAM retention voltage (VRAM) < VBOR 4
Delay after device exits reset state TBORD 10 20 µs VDD > VBOR 4
Supply current, 3.4 MHz IDD 600 µA Serial interface active, write all 0's to volatile wiper 0, VDD = 5.5V, FSCL = 3.4 MHz 4
Supply current, 100 kHz IDD 250 µA Serial interface active, write all 0's to volatile wiper 0, VDD = 5.5V, FSCL = 100 kHz 4
Supply current, serial interface inactive IDD 2.5 5 µA Stop condition, SCL = SDA = VIH, wiper = 0, VDD = 5.5V, HVC/A0 = VIH 4
Wiper resistance, 5.5V RW 75 160 Ω VDD = 5.5 V, IW = 2.0 mA, code = 00h 5
Wiper resistance, 2.7V RW 75 300 Ω VDD = 2.7 V, IW = 2.0 mA, code = 00h 5
Nominal resistance match (MCP46X2) /RBW0-RBW1//RBW 0.25 1.5 % MCP46X2 devices only, Code = Full-Scale 5
Resistor terminal input voltage range VA,VW,VB 0 5.5 V Note 5, Note 6; min printed as Vss, max as VDD 5
Max current through terminal A, W or B IT 2.5 mA Terminal W IAW or IBW, W = FS or ZS 6
Max current through terminals A and B IAB 0.069 mA IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 80000 6
Rheostat INL, 8-bit 5.5V R-INL -1 0.5 1 LSb MCP4XX2, 100 k 8-bit, 5.5V, IW = 45 µA (typ printed ±0.5) 9
Rheostat INL, 8-bit 3.0V R-INL -1.5 0.25 1.5 LSb MCP4XX2, 100 k 8-bit, 3.0V, IW = 24 µA (Note 7) 9
Rheostat DNL, 8-bit 5.5V R-DNL -0.5 0.25 0.5 LSb MCP4XX2, 100 k 8-bit, 5.5V, IW = 45 µA (typ printed ±0.25) 10
Rheostat DNL, 8-bit 3.0V R-DNL -0.5 0.25 0.5 LSb MCP4XX2, 100 k 8-bit, 3.0V, IW = 24 µA (Note 7; typ printed ±0.25) 10
Schmitt trigger high input threshold, 2.7-5.5V VIH 0.45 VDD All inputs except SDA and SCL, 2.7V ≤ VDD ≤ 5.5V 11
Schmitt trigger high input threshold, 1.8-2.7V VIH 0.5 VDD All inputs except SDA and SCL, 1.8V ≤ VDD ≤ 2.7V 11
Schmitt trigger high input threshold (SDA, SCL) VIH 0.7 VDD SDA and SCL, 100 kHz, 400 kHz, 1.7 MHz and 3.4 MHz 11
Schmitt trigger low input threshold VIL 0.2 VDD All inputs except SDA and SCL 11
Schmitt trigger low input threshold (SDA, SCL) VIL -0.5 0.3 V SDA and SCL, all modes; max printed as 0.3VDD 11
High voltage limit VMAX 12.5 V Pin can tolerate VMAX or less 11
Output low voltage (SDA), VDD < 2.0V VOL 0 0.2 V VDD < 2.0V, IOL = 1 mA; min printed VSS, max 0.2VDD 12
Output low voltage (SDA), VDD ≥ 2.0V VOL 0 0.4 V VDD ≥ 2.0V, IOL = 3 mA; min printed VSS 12
Weak pull-up / pull-down current IPU 1.75 mA Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VIHH = 12.5V 12
Input leakage current IIL -1 1 µA VIN = VDD and VIN = VSS 12
Power supply sensitivity (8-bit) PSS 0.0015 0.0035 %/% 8-bit, VDD = 2.7V to 5.5V, VA = 2.7V, Code = 80h 12
SCL clock frequency, standard mode FSCL 0 100 kHz Cb = 400 pF, 1.8V - 5.5V 13
SCL clock frequency, fast mode FSCL 0 400 kHz Cb = 400 pF, 2.7V - 5.5V 13
SCL clock frequency, high-speed 1.7 FSCL 0 1.7 MHz Cb = 400 pF, 4.5V - 5.5V 13
SCL clock frequency, high-speed 3.4 FSCL 0 3.4 MHz Cb = 100 pF, 4.5V - 5.5V 13
START condition setup time, 100 kHz TSU:STA 4700 ns 100 kHz mode 13
START condition hold time, 100 kHz THD:STA 4000 ns 100 kHz mode 13
Clock high time, 3.4 MHz THIGH 60 ns 3.4 MHz mode, 4.5V-5.5V 14
Clock low time, 3.4 MHz TLOW 160 ns 3.4 MHz mode, 4.5V-5.5V 14
Data input setup time, 3.4 MHz TSU:DAT 10 ns 3.4 MHz mode 15
Output valid from clock, 3.4 MHz TAA 150 ns 3.4 MHz mode, Cb = 100 pF, Note 1 15
Voltage on VDD VDD -0.6 7 V with respect to VSS 3
Voltage on HVC/A0, A1, A2, SCL, SDA -0.6 12.5 V with respect to VSS 3
Input clamp current IIK -20 20 mA VI < 0, VI > VDD, VI > VPP on HV pins 3
Output clamp current IOK -20 20 mA VO < 0 or VO > VDD 3
Maximum current into PxA, PxW, PxB -2.5 2.5 mA 3
Storage temperature -65 150 °C 3
Maximum junction temperature TJ 150 °C 3
Thermal resistance, 10L-DFN (3x3) θJA 57 °C/W 16
Nominal resistance tempco, -20 to 70°C ΔRAB/ΔT 50 ppm/°C TA = -20°C to +70°C 5
Nominal resistance tempco, -40 to 85°C ΔRAB/ΔT 100 ppm/°C TA = -40°C to +85°C 5
Nominal resistance tempco, -40 to 125°C ΔRAB/ΔT 150 ppm/°C TA = -40°C to +125°C 5
Bandwidth -3 dB, 100 k 8-bit BW 100 kHz 100 k 8-bit, Code = 80h, load = 30 pF 8
Capacitance (PA) CAW 75 pF f = 1 MHz, Code = Full-Scale 10
Capacitance (PW) CW 120 pF f = 1 MHz, Code = Full-Scale 10
Capacitance (PB) CBW 75 pF f = 1 MHz, Code = Full-Scale 10
Hysteresis of Schmitt trigger inputs VHYS 0.1 VDD All inputs except SDA and SCL 11
Leakage current into A, W or B IWL 100 nA MCP4XX2 PxB = PxW = VSS 6
HVC pull-up / pull-down resistance RHVC 16 kΩ VDD = 5.5V, VHVC = 3V 12
Pin capacitance CIN, COUT 10 pF fC = 3.4 MHz 12

CAD (KiCad official)

  • Symbol: MCP4652T-104E
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: mcp4652t-104e-etched.step / mcp4652t-104e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp4652t-104e.step / mcp4652t-104e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (102 pp, sha256 ee77464c39584a73, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF