component
MCP45HV51-502E
Public Made by Adomby adom
Microchip Tech Digital Potentiometers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMCP45HV51-502E
Microchip Tech · Digital Potentiometers · TSSOP-14
MCP45HV51-502E from Microchip Tech, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VL | power_in | Positive digital power supply input, relative to DGND, ranging from 1.8V to 5.5V, with a decoupling capacitor to DGND recommended. |
| 2 | SCL | input | I2C serial clock input (Schmitt trigger); the device is an I2C client so this pin is input-only. |
| 3 | A1 | input | I2C address bit 1 input (Schmitt trigger); with A0 allows up to four devices on one I2C bus. |
| 4 | SDA | bidirectional | I2C serial data input/output (Schmitt trigger) with an open-drain N-channel driver. |
| 5 | A0 | input | I2C address bit 0 input (Schmitt trigger), latched at POR/BOR. |
| 6 | WLAT | input | Wiper latch enable input: 0 transfers the received I2C shift-register value to the Wiper register, 1 holds the received value in the shift register buffer. |
| 7 | NC | unconnected | Not internally connected to the die; connect to DGND or VL to reduce noise coupling. |
| 8 | SHDN | input | Shutdown input (Schmitt trigger) that forces the resistor network terminals into the hardware shutdown state. |
| 9 | DGND | power_in | Digital ground reference for the device. |
| 10 | V- | power_in | Analog negative supply; its potential must be lower than or equal to the DGND potential. |
| 11 | P0B | passive | Potentiometer 0 Terminal B (zero-scale wiper end, code 0x00); no polarity, voltage must be between V+ and V-. |
| 12 | P0W | passive | Potentiometer 0 wiper terminal; no polarity, voltage must be between V+ and V-. |
| 13 | P0A | passive | Potentiometer 0 Terminal A (full-scale wiper end, 0xFF for 8-bit); no polarity, voltage must be between V+ and V-. |
| 14 | V+ | power_in | Analog positive supply, which must be at a higher potential than the V- pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TSSOP-14 |
| Category | ADC/DAC/Data Conversion |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal resistance A-B (-502) | RAB | 4 | 5 | 6 | kΩ | -502 devices, V+/V- = 10V to 36V | 5 |
| Digital supply voltage | VL | 2.7 | 5.5 | V | With respect to DGND | 4 | |
| Digital supply voltage (VL ≥ V- + 2.7V) | VL | 1.8 | 5.5 | V | VL ≥ V- + 2.7V | 4 | |
| Analog positive supply voltage | V+ | 36 | V | With respect to V- | 4 | ||
| Resistor network supply voltage | VRN | 36 | V | Delta voltage between V+ and V- | 4 | ||
| VL start voltage to ensure wiper reset | VDPOR | 1.8 | V | With respect to DGND, V+ > 6.0V | 4 | ||
| V+ voltage to ensure wiper reset | VAPOR | 6 | V | With respect to V-, VL = 0V | 4 | ||
| Delay after exit from reset | TBORD | 10 | 20 | µs | VL > VBOR | 5 | |
| Supply current, serial interface active | IDDD | 45 | 650 | µA | Write all 0's to Volatile Wiper 0; VL = 5.5V, FSCL = 3.4 MHz, V- = DGND | 5 | |
| Supply current, serial interface inactive | IDDD | 4 | 7 | µA | VL = 5.5V, SCL = VIH, Wiper = 0, V- = DGND | 5 | |
| Analog supply current V+ to V- | IDDA | 5 | µA | PxA = PxB = PxW, DGND = V- +(V+/2) | 5 | ||
| RAB current | IAB | 9 | mA | -502 devices 36V / RAB(MIN), V- = -18V, V+ = +18V | 5 | ||
| Wiper resistance | RW | 75 | 170 | Ω | IW = 1 mA, V+ = +18V, V- = -18V, code = 00h, PxA = floating, PxB = V- | 6 | |
| Wiper resistance | RW | 145 | 200 | Ω | IW = 1 mA, V+ = +5.0V, V- = -5.0V, code = 00h, PxA = floating, PxB = V- | 6 | |
| Nominal resistance tempco | ΔRAB/ΔT | 50 | ppm/°C | TA = -40°C to +85°C | 6 | ||
| Nominal resistance tempco | ΔRAB/ΔT | 100 | ppm/°C | TA = -40°C to +125°C | 6 | ||
| Ratiometric tempco | ΔVBW/ΔT | 15 | ppm/°C | Code = Mid scale (7Fh or 3Fh) | 6 | ||
| Current through terminals A, B, W | IT, IW | 25 | mA | -502 devices IBW(W ≠ ZS) and IAW(W ≠ FS) | 6 | ||
| Current through terminals at ZS/FS | IT, IW | 36 | mA | IBW(W = ZS), or IAW(W = FS) | 6 | ||
| Full scale error 5k 8-bit | VWFSE | -10.5 | LSb | 5 k 8-bit VAB = 20V to 36V | 7 | ||
| Zero scale error 5k 8-bit | VWZSE | 9.5 | LSb | 5 k 8-bit VAB = 20V to 36V | 8 | ||
| Potentiometer INL 5k 8-bit | P-INL | -1 | 0.5 | 1 | LSb | 5 k 8-bit VAB = 10V to 36V | 9 |
| Potentiometer DNL 5k 8-bit | P-DNL | -0.7 | 0.25 | 0.7 | LSb | 5 k 8-bit VAB = 10V to 36V | 9 |
| Rheostat INL 5k 8-bit | R-INL | -2 | 2 | LSb | 5 k 8-bit IW = 6.0 mA, (V+ - V-) = 36V (Note 2) | 11 | |
| Rheostat INL 5k 8-bit | R-INL | -2.5 | 2.5 | LSb | IW = 3.3 mA, (V+ - V-) = 20V (Note 2) | 11 | |
| Rheostat INL 5k 8-bit | R-INL | -4.5 | 4.5 | LSb | IW = 1.7 mA, (V+ - V-) = 10V | 11 | |
| Rheostat DNL 5k 8-bit | R-DNL | -0.5 | 0.5 | LSb | 5 k 8-bit IW = 6.0 mA, (V+ - V-) = 36V (Note 2) | 12 | |
| Rheostat DNL 5k 8-bit | R-DNL | -0.8 | 0.8 | LSb | IW = 1.7 mA, (V+ - V-) = 10V | 12 | |
| Schmitt trigger high-input threshold | VIH | 0.7 | x VL | 1.8V ≤ VL ≤ 5.5V; printed min 0.7 VL, max VL + 0.3V | 13 | ||
| Schmitt trigger low-input threshold | VIL | 0.3 | x VL | Printed max 0.3 VL; min DGND - 0.5V | 13 | ||
| Output low voltage (SDA) | VOL | 0.2 | x VL | VL = 5.5V, IOL = 5 mA | 13 | ||
| Input leakage current | IIL | -1 | 1 | µA | VIN = VL and VIN = DGND | 13 | |
| Power supply sensitivity 8-bit | PSS | 0.0015 | 0.0035 | %/% | VL = 2.7V to 5.5V, V+ = 18V, V- = -18V, Code = 7Fh | 14 | |
| Bandwidth -3 dB 5k 8-bit | BW | 480 | kHz | 5 k 8-bit Code = 7Fh, load = 30 pF | 10 | ||
| VW settling time 5k | tS | 1 | µs | 5 k Code = 00h -> FFh (7Fh); VA = 10V, VB = 0V, CL = 50 pF | 10 | ||
| Power dissipation 5k | PDISS | 260 | mW | 5 k VL = 5.5V, V+ = 18V, V- = -18V | 14 | ||
| Voltage on VL with respect to DGND | -0.6 | 7 | V | 3 | |||
| Voltage on V+ with respect to V- | 40 | V | 3 | ||||
| Maximum continuous current into PxA, PxW, PxB (5 k) | -25 | 25 | mA | RAB = 5 k | 3 | ||
| Package power dissipation TSSOP-14 | 1000 | mW | TA = +50°C, TJ = +150°C | 3 | |||
| ESD HBM | -5 | 5 | kV | All pins | 3 | ||
| Maximum junction temperature | TJ | 150 | °C | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Ambient temperature with power applied | -40 | 125 | °C | 3 | |||
| Operating temperature range | TA | -40 | 125 | °C | 21 | ||
| Thermal resistance 14L-TSSOP | θJA | 100 | °C/W | 21 |
CAD (KiCad official)
- Symbol:
MCP45HV51-502E - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
mcp45hv51-502e-etched.step/mcp45hv51-502e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp45hv51-502e.step/mcp45hv51-502e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (102 pp, sha256
18feae380a4045ff, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).