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MCP45HV31-104E
Public Made by Adomby adom
Microchip Tech Digital Potentiometers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMCP45HV31-104E
Microchip Tech · Digital Potentiometers · TSSOP-14
MCP45HV31-104E from Microchip Tech, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VL | power_in | Positive digital power supply input, referenced to DGND, specified from 1.8V to 5.5V; a decoupling capacitor to DGND is recommended for maximum performance. |
| 2 | SCL | input | I2C serial clock input (Schmitt trigger); the device is an I2C slave, so this pin is input-only. |
| 3 | A1 | input | I2C address bit 1 input (Schmitt trigger), latched at POR/BOR; together with A0 it allows up to four devices on one I2C bus. |
| 4 | SDA | bidirectional | I2C serial data pin, an open-drain N-channel driver that lets the host read and write the Wiper and TCON registers. |
| 5 | A0 | input | I2C address bit 0 input (Schmitt trigger), latched at POR/BOR; together with A1 it completes the device address. |
| 6 | WLAT | input | Wiper latch enable: when Low, the received I2C value is transferred from the shift buffer to the Wiper register; when High, the value is held in the shift buffer (SPBUF). |
| 7 | NC | unconnected | Not internally connected to the die; to reduce noise coupling, connect to DGND or VL. |
| 8 | SHDN | input | Shutdown input (Schmitt trigger) that forces the resistor network terminals into the hardware shutdown state. |
| 9 | DGND | power_in | Digital ground reference for the device; VL and the level-shifted digital signals are referenced to this pin. |
| 10 | V- | power_in | Analog negative potential supply; must be lower than or equal to the DGND pin potential. |
| 11 | P0B | passive | Potentiometer 0 Terminal B, the zero-scale wiper connection; the voltage must be between V- and V+ and it can carry positive or negative current. |
| 12 | P0W | passive | Potentiometer 0 wiper (W) terminal; the voltage must be between V- and V+ and it can carry positive or negative current. |
| 13 | P0A | passive | Potentiometer 0 Terminal A, the full-scale wiper connection; the voltage must be between V- and V+ and it can carry positive or negative current. |
| 14 | V+ | power_in | Analog positive potential supply, which must be at a higher potential than V-; analog operation is specified from 10V to 36V with a maximum of +36V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TSSOP-14 |
| Category | ADC/DAC/Data Conversion |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Digital Positive Supply Voltage (VL) | VL | 2.7 | 5.5 | V | With respect to DGND (Note 4) | 4 | |
| Digital Positive Supply Voltage (VL), 1.8V operation | VL | 1.8 | 5.5 | V | VL ≥ V- + 2.7V (Note 1, Note 4) | 4 | |
| Digital to Analog Level Shifter Operational Voltage | VLS | 2.3 | V | VL to V- voltage | 4 | ||
| Analog Positive Supply Voltage (V+) | V+ | 36 | V | With respect to V- (Note 4) | 4 | ||
| Analog Negative Supply Voltage (V-) | V- | 0 | V | With respect to DGND and with VL = 1.8V | 4 | ||
| Resistor Network Supply Voltage | VRN | 36 | V | Delta voltage between V+ and V- (Note 4) | 4 | ||
| VL Start Voltage to ensure Wiper Reset | VDPOR | 1.8 | V | With respect to DGND, V+ > 6.0V | 4 | ||
| V+ Voltage to ensure Wiper Reset | VAPOR | 6 | V | With respect to V-, VL = 0V | 4 | ||
| Delay after device exits the Reset state | TBORD | 10 | 20 | µs | VL > VBOR | 5 | |
| Supply Current, serial interface active | IDDD | 45 | 650 | µA | Serial Interface Active, Write all 0's to Volatile Wiper 0 (address 0h), VL = 5.5V, FSCL = 3.4 MHz, V- = DGND | 5 | |
| Supply Current, serial interface inactive | IDDD | 4 | 7 | µA | Serial Interface Inactive, VL = 5.5V, SCL = VIH, Wiper = 0, V- = DGND | 5 | |
| Supply Current, analog | IDDA | 5 | µA | Current V+ to V-, PxA = PxB = PxW, DGND = V- +(V+/2) | 5 | ||
| Resistance RAB (-104 device) | RAB | 80 | 100 | 120 | kΩ | -104 devices, V+/V- = 10V to 36V | 5 |
| RAB resistance tolerance | RAB | -20 | 20 | % | Resistance (± 20%) as printed for RAB | 5 | |
| RAB Current (-104 device) | IAB | 0.45 | mA | -104 devices, 36V / RAB(MIN), V- = -18V, V+ = +18V (Note 9) | 5 | ||
| Wiper Resistance | RW | 75 | 170 | Ω | IW = 1 mA V+ = +18V, V- = -18V, code = 00h, PxA = floating, PxB = V- | 6 | |
| Wiper Resistance | RW | 145 | 200 | Ω | IW = 1 mA V+ = +5.0V, V- = -5.0V, code = 00h, PxA = floating, PxB = V- (Note 2) | 6 | |
| Terminal Current (A, B, Wiper) | IT, IW | 6.5 | mA | -104 devices IBW(W ≠ ZS) and IAW(W ≠ FS) | 6 | ||
| Terminal Current (A, B, Wiper), zero/full scale | IT, IW | 36 | mA | IBW(W = ZS), or IAW(W = FS) | 6 | ||
| Full Scale Error (Potentiometer), 7-bit, 100 k | VWFSE | -0.85 | LSb | 7-bit, VAB = 20V to 36V | 7 | ||
| Full Scale Error (Potentiometer), 7-bit, 100 k | VWFSE | -0.975 | LSb | 7-bit, VAB = 10V to 36V | 7 | ||
| Zero Scale Error (Potentiometer), 7-bit, 100 k | VWZSE | 0.3 | LSb | 7-bit, VAB = 20V to 36V | 8 | ||
| Zero Scale Error (Potentiometer), 7-bit, 100 k | VWZSE | 0.475 | LSb | 7-bit, VAB = 10V to 36V | 8 | ||
| Potentiometer Integral Nonlinearity, 7-bit, 100 k | P-INL | -1 | 0.5 | 1 | LSb | 7-bit, VAB = 10V to 36V | 9 |
| Potentiometer Differential Nonlinearity, 7-bit, 100 k | P-DNL | -0.125 | 0.1 | 0.125 | LSb | 7-bit, VAB = 10V to 36V | 9 |
| Rheostat Integral Nonlinearity, 7-bit, 100 k | R-INL | -0.5 | 0.5 | LSb | 7-bit, IW = 300 µA, (V+ - V-) = 36V (Note 2) | 11 | |
| Rheostat Integral Nonlinearity, 7-bit, 100 k | R-INL | -0.6 | 0.6 | LSb | 7-bit, IW = 83 µA, (V+ - V-) = 10V | 11 | |
| Rheostat Differential Nonlinearity, 7-bit, 100 k | R-DNL | -0.25 | 0.25 | LSb | 7-bit, IW = 300 µA, (V+ - V-) = 36V (Note 2) | 12 | |
| Power Supply Sensitivity, 7-bit | PSS | 0.0015 | 0.0035 | %/% | 7-bit, VL = 2.7V to 5.5V, V+ = 18V, V- = -18V, Code = 3Fh | 14 | |
| Input Leakage Current | IIL | -1 | 1 | uA | VIN = VL and VIN = DGND | 13 | |
| I2C clock frequency, High Speed 3.4 MHz mode | FSCL | 0 | 3.4 | MHz | Cb = 100 pF, 4.5V ≤ VL ≤ 5.5V | 17 | |
| Specified Temperature Range | TA | -40 | 125 | °C | Extended temperature grade (E) | 21 | |
| Voltage on V- with respect to DGND | V- | -40 | 0.6 | V | Printed as DGND + 0.6V max to -40.0V min | 3 | |
| Voltage on V+ with respect to DGND | V+ | -0.3 | 40 | V | Printed as DGND - 0.3V to 40.0V | 3 | |
| Voltage on V+ with respect to V- | V+ | -0.3 | 40 | V | Printed as DGND - 0.3V to 40.0V | 3 | |
| Voltage on VL with respect to V+ | VL | -40 | -0.6 | V | 3 | ||
| Voltage on VL with respect to V- | VL | -0.6 | 40 | V | 3 | ||
| Voltage on VL with respect to DGND | VL | -0.6 | 7 | V | 3 | ||
| Voltage on SCL, SDA, A0, A1, WLAT, SHDN with respect to DGND | -0.6 | V | Upper limit VL + 0.6V | 3 | |||
| Voltage on PxA, PxW, PxB with respect to V- | -0.3 | V | Upper limit V+ + 0.3V | 3 | |||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0, VI > VL, VI > VPP on HV pins | 3 | |
| Maximum current out of DGND pin | 100 | mA | 3 | ||||
| Maximum current into VL pin | 100 | mA | 3 | ||||
| Maximum current out of V- pin | 100 | mA | 3 | ||||
| Maximum current into V+ pin | 100 | mA | 3 | ||||
| Maximum current into PXA, PXW, PXB pins (Continuous) | -6.5 | 6.5 | mA | RAB = 100 k | 3 | ||
| Maximum output current sunk by any Output pin | 25 | mA | 3 | ||||
| Maximum output current sourced by any Output pin | 25 | mA | 3 | ||||
| Package Power Dissipation, TSSOP-14 | 1000 | mW | TA = +50°C, TJ = +150°C | 3 | |||
| ESD protection, Human Body Model (HBM) | -5 | 5 | kV | Human Body Model (HBM) | 3 | ||
| Maximum Junction Temperature (TJ) | TJ | 150 | °C | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Ambient temperature with power applied | -40 | 125 | °C | 3 | |||
| Thermal Resistance, 14L-TSSOP (ST) | JA | 100 | °C/W | 14L-TSSOP (ST) | 21 | ||
| Nominal Resistance Tempco, TA = -40°C to +85°C | RAB/T | 50 | ppm/°C | TA = -40°C to +85°C | 6 | ||
| Nominal Resistance Tempco, TA = -40°C to +125°C | RAB/T | 100 | ppm/°C | TA = -40°C to +125°C | 6 | ||
| Ratiometric Tempco | VBW/T | 15 | ppm/°C | Code = Mid scale (7Fh or 3Fh) | 6 |
CAD (KiCad official)
- Symbol:
MCP45HV31-104E - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
mcp45hv31-104e-etched.step/mcp45hv31-104e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp45hv31-104e.step/mcp45hv31-104e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (100 pp, sha256
ab854db7c83242c1, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).