component
MCP4531-503E
Public Made by Adomby adom
Microchip Tech Digital Potentiometers, MSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MCP4531-503E
Microchip Tech · Digital Potentiometers · MSOP-8
MCP4531-503E from Microchip Tech, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HVC/A0 | input | High Voltage Command / Address 0 input, whose value is latched at POR/BOR for the I2C address, and when driven at VIHH it selects High Voltage command mode. |
| 2 | SCL | input | I2C serial clock input that accepts only external clock signals from the host, as a high-voltage tolerant input with Schmitt trigger. |
| 3 | SDA | bidirectional | I2C serial data I/O implemented as an open-drain N-channel driver, as a high-voltage tolerant input with Schmitt trigger. |
| 4 | VSS | power_in | Device ground reference. |
| 5 | P0A | passive | Potentiometer 0 terminal A, the fixed connection to the full-scale wiper value (0x80 for 7-bit devices), with voltage that must be between VSS and VDD. |
| 6 | P0W | passive | Potentiometer 0 wiper terminal, which may carry positive or negative current, with voltage that must be between VSS and VDD. |
| 7 | P0B | passive | Potentiometer 0 terminal B, the fixed connection to the zero-scale wiper value (0x00), with voltage that must be between VSS and VDD. |
| 8 | VDD | power_in | Positive power supply input relative to VSS; electrical performance may not meet the data sheet specifications while VDD is below 2.7V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | MSOP-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (device characteristics specified) | VDD | 2.7 | 5.5 | V | 4 | ||
| Supply voltage (serial interface only) | VDD | 1.8 | 2.7 | V | Serial interface only | 4 | |
| HVC pin voltage range (upper limit) | VHV | 12.5 | V | VDD >= 4.5V | 4 | ||
| VDD start voltage to ensure wiper reset | VBOR | 1.65 | V | RAM retention voltage (VRAM) < VBOR | 4 | ||
| Delay after device exits reset state | TBORD | 10 | 20 | µs | VDD > VBOR | 4 | |
| Supply current, serial interface active, FSCL 3.4 MHz | IDD | 600 | µA | Serial interface active, HVC/A0 = VIH (or VIL); write all 0's to volatile wiper 0; VDD = 5.5V, FSCL = 3.4 MHz | 4 | ||
| Supply current, serial interface active, FSCL 100 kHz | IDD | 250 | µA | Serial interface active, HVC/A0 = VIH (or VIL); write all 0's to volatile wiper 0; VDD = 5.5V, FSCL = 100 kHz | 4 | ||
| Supply current, serial interface inactive | IDD | 2.5 | 5 | µA | Serial interface inactive (stop condition, SCL = SDA = VIH); wiper = 0; VDD = 5.5V, HVC/A0 = VIH | 4 | |
| Nominal resistance RAB (-503 device, 50 kOhm) | RAB | 40 | 50 | 60 | kΩ | -503 devices; resistance between terminal A and B | 5 |
| Resistance tolerance | RAB | -20 | 20 | % | (±20%) | 5 | |
| Wiper resistance RW, VDD 5.5V | RW | 75 | 160 | Ω | VDD = 5.5 V, IW = 2.0 mA, code = 00h | 5 | |
| Wiper resistance RW, VDD 2.7V | RW | 75 | 300 | Ω | VDD = 2.7 V, IW = 2.0 mA, code = 00h | 5 | |
| Full-scale error VWFSE, 50 kOhm, 7-bit | VWFSE | -0.5 | -0.1 | LSb | 7-bit, 3.0V <= VDD <= 5.5V | 7 | |
| Zero-scale error VWZSE, 50 kOhm, 7-bit | VWZSE | 0.1 | 0.5 | LSb | 7-bit, 3.0V <= VDD <= 5.5V | 7 | |
| Potentiometer integral non-linearity, 7-bit | INL | -0.5 | 0.25 | 0.5 | LSb | 7-bit; MCP4XX1 devices only | 7 |
| Potentiometer differential non-linearity, 7-bit | DNL | -0.25 | 0.125 | 0.25 | LSb | 7-bit; MCP4XX1 devices only | 7 |
| Rheostat integral non-linearity, 50 kOhm, 7-bit, 5.5V | R-INL | -1.125 | 0.5 | 1.125 | LSb | 7-bit, 5.5V, IW = 90 µA | 9 |
| Rheostat integral non-linearity, 50 kOhm, 7-bit, 3.0V | R-INL | -1.5 | 1 | 1.5 | LSb | 7-bit, 3.0V, IW = 48 µA | 9 |
| Rheostat differential non-linearity, 50 kOhm, 7-bit, 5.5V | R-DNL | -0.375 | 0.25 | 0.375 | LSb | 7-bit, 5.5V, IW = 90 µA | 10 |
| Rheostat differential non-linearity, 50 kOhm, 7-bit, 3.0V | R-DNL | -0.375 | 0.25 | 0.375 | LSb | 7-bit, 3.0V, IW = 48 µA | 10 |
| Maximum current, terminal A (wiper at full scale) | IT | 2.5 | mA | Terminal A IAW, W = full-scale (FS) | 6 | ||
| Maximum current, terminal B (wiper at zero scale) | IT | 2.5 | mA | Terminal B IBW, W = zero-scale (ZS) | 6 | ||
| Maximum current, terminal W | IT | 2.5 | mA | Terminal W IAW or IBW, W = FS or ZS | 6 | ||
| Maximum current, terminals A to B (50 kOhm) | IAB | 0.138 | mA | IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 40000 | 6 | ||
| High voltage limit on digital inputs | VMAX | 12.5 | V | Pin can tolerate VMAX or less | 11 | ||
| Output low voltage (SDA) | VOL | 0.4 | V | VDD >= 2.0V, IOL = 3 mA | 12 | ||
| Weak pull-up / pull-down current | IPU | 1.75 | mA | Internal VDD pull-up, VIHH pull-down; VDD = 5.5V, VIHH = 12.5V | 12 | ||
| Input leakage current | IIL | -1 | 1 | µA | VIN = VDD and VIN = VSS | 12 | |
| I2C clock frequency, standard mode | FSCL | 0 | 100 | kHz | Cb = 400 pF, 1.8V - 5.5V | 13 | |
| I2C clock frequency, fast mode | FSCL | 0 | 400 | kHz | Cb = 400 pF, 2.7V - 5.5V | 13 | |
| I2C clock frequency, high-speed 1.7 MHz | FSCL | 0 | 1.7 | MHz | Cb = 400 pF, 4.5V - 5.5V | 13 | |
| I2C clock frequency, high-speed 3.4 MHz | FSCL | 0 | 3.4 | MHz | Cb = 100 pF, 4.5V - 5.5V | 13 | |
| Output valid from clock (TAA), 100 kHz mode | TAA | 3450 | ns | 100 kHz mode; Note 1 | 15 | ||
| Output valid from clock (TAA), 400 kHz mode | TAA | 900 | ns | 400 kHz mode; Note 1 | 15 | ||
| Bus free time (TBUF), 100 kHz mode | TBUF | 4700 | ns | Time the bus must be free before a new transmission can start; 100 kHz mode | 15 | ||
| Bus free time (TBUF), 400 kHz mode | TBUF | 1300 | ns | Time the bus must be free before a new transmission can start; 400 kHz mode | 15 | ||
| Voltage on VDD with respect to VSS | -0.6 | 7 | V | 3 | |||
| Voltage on HVC/A0, A1, A2, SCL and SDA with respect to VSS | -0.6 | 12.5 | V | 3 | |||
| Voltage on PxA, PxW and PxB with respect to VSS | -0.3 | V | Maximum printed as VDD + 0.3V | 3 | |||
| Input clamp current IIK | IIK | -20 | 20 | mA | VI < 0, VI > VDD, VI > VPP on HV pins | 3 | |
| Output clamp current IOK | IOK | -20 | 20 | mA | VO < 0 or VO > VDD | 3 | |
| Maximum output current sunk by any output pin | 25 | mA | 3 | ||||
| Maximum output current sourced by any output pin | 25 | mA | 3 | ||||
| Maximum current out of VSS pin | 100 | mA | 3 | ||||
| Maximum current into VDD pin | 100 | mA | 3 | ||||
| Maximum current into PXA, PXW and PXB pins | -2.5 | 2.5 | mA | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Ambient temperature with power applied | -40 | 125 | °C | 3 | |||
| Maximum junction temperature (TJ) | TJ | 150 | °C | 3 | |||
| ESD protection on all pins, HBM | 4 | kV | HBM | 3 | |||
| ESD protection on all pins, MM | 300 | V | MM | 3 | |||
| Operating temperature range | TA | -40 | 125 | °C | 16 | ||
| Thermal resistance, 8L-MSOP | JA | 211 | °C/W | 16 | |||
| Nominal resistance tempco, TA -20°C to +70°C | RAB/T | 50 | ppm/°C | TA = -20°C to +70°C | 5 | ||
| Nominal resistance tempco, TA -40°C to +85°C | RAB/T | 100 | ppm/°C | TA = -40°C to +85°C | 5 | ||
| Nominal resistance tempco, TA -40°C to +125°C | RAB/T | 150 | ppm/°C | TA = -40°C to +125°C | 5 | ||
| Ratiometric tempco | VWB/T | 15 | ppm/°C | Code = midscale (80h or 40h) | 5 |
CAD (KiCad official)
- Symbol:
MCP4531-503E - Footprint:
Package_SO:MSOP-8_3x3mm_P0.65mm - 3D model: MSOP-8 (KiCad packages3D, STEP)
- 3D model files:
mcp4531-503e-etched.step/mcp4531-503e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4531-503e.step/mcp4531-503e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (102 pp, sha256
ee77464c39584a73, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).