# MCP4462-103E

**Microchip Tech** · Digital Potentiometers · TSSOP-14

MCP4462-103E from Microchip Tech, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P3W | passive | Potentiometer 3 wiper terminal, analog pin whose voltage must be between VSS and VDD. |
| 2 | P3B | passive | Potentiometer 3 terminal B (zero-scale end, wiper value 0x00), analog pin with no polarity whose voltage must be between VSS and VDD. |
| 3 | HVC/A0 | input | High Voltage Command / I2C Address 0 input; A0 is latched at POR/BOR and a voltage of VIHH selects a high-voltage command. |
| 4 | SCL | input | I2C serial clock input (high-voltage tolerant with Schmitt trigger), connected to the host controller SCL; the device is a slave. |
| 5 | SDA | bidirectional | I2C serial data I/O (high-voltage tolerant with Schmitt trigger) with an open-drain N-channel output. |
| 6 | VSS | power_in | Ground reference for the device. |
| 7 | P1B | passive | Potentiometer 1 terminal B (zero-scale end), analog pin whose voltage must be between VSS and VDD. |
| 8 | P1W | passive | Potentiometer 1 wiper terminal, analog pin whose voltage must be between VSS and VDD. |
| 9 | P0W | passive | Potentiometer 0 wiper terminal, analog pin whose voltage must be between VSS and VDD. |
| 10 | P0B | passive | Potentiometer 0 terminal B (zero-scale end), analog pin whose voltage must be between VSS and VDD. |
| 11 | A1 | input | I2C Address 1 input (high-voltage tolerant with Schmitt trigger and smart pull-up); with A0 allows up to 4 devices on one I2C bus. |
| 12 | VDD | power_in | Positive power supply input relative to VSS; specifications are guaranteed for 2.7V to 5.5V, with operation from 1.8V. |
| 13 | P2B | passive | Potentiometer 2 terminal B (zero-scale end), analog pin whose voltage must be between VSS and VDD. |
| 14 | P2W | passive | Potentiometer 2 wiper terminal, analog pin whose voltage must be between VSS and VDD. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TSSOP-14 |
| Category | ADC/DAC/Data Conversion |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 2.7 |  | 5.5 | V |  | 4 |
| Supply voltage, serial interface only | VDD | 1.8 |  | 2.7 | V | Serial Interface only | 4 |
| Nominal resistance RAB | RAB | 8 | 10 | 12 | kΩ | -103 devices (Note 1), ±20% | 5 |
| Resistance tolerance |  | -20 |  | 20 | % | Resistance (± 20%) | 5 |
| Wiper resistance | RW |  | 75 | 160 | Ω | VDD = 5.5 V, IW = 2.0 mA, code = 00h | 5 |
| Wiper resistance | RW |  | 75 | 300 | Ω | VDD = 2.7 V, IW = 2.0 mA, code = 00h | 5 |
| Nominal resistance tempco | ΔRAB/ΔT |  | 50 |  | ppm/°C | TA = -20°C to +70°C | 5 |
| Nominal resistance tempco | ΔRAB/ΔT |  | 100 |  | ppm/°C | TA = -40°C to +85°C | 5 |
| Nominal resistance tempco | ΔRAB/ΔT |  | 150 |  | ppm/°C | TA = -40°C to +125°C | 5 |
| Ratiometric tempco | ΔVWB/ΔT |  | 15 |  | ppm/°C | Code = Midscale (80h or 40h) | 5 |
| Rheostat INL, 10 kΩ 8-bit | R-INL | -1.5 | 0.5 | 1.5 | LSb | 5.5V, IW = 450 µA | 8 |
| Rheostat INL, 10 kΩ 8-bit | R-INL | -5.5 | 2.5 | 5.5 | LSb | 3.0V, IW = 240 µA (Note 7) | 8 |
| Rheostat DNL, 10 kΩ 8-bit | R-DNL | -0.5 | 0.25 | 0.5 | LSb | 5.5V, IW = 450 µA | 9 |
| Rheostat DNL, 10 kΩ 8-bit | R-DNL | -1 | 0.25 | 1 | LSb | 3.0V, IW = 240 µA (Note 7) | 9 |
| Supply current, serial active 3.4 MHz | IDD |  |  | 600 | µA | Serial Interface Active, write all 0's to volatile Wiper 0, VDD = 5.5V, FSCL @ 3.4 MHz | 4 |
| Supply current, serial active 100 kHz | IDD |  |  | 250 | µA | Serial Interface Active, write all 0's to volatile Wiper 0, VDD = 5.5V, FSCL @ 100 kHz | 4 |
| Supply current, EE write | IDD |  |  | 575 | µA | EE Write Current, VDD = 5.5V, FSCL = 400 kHz, write all 0's to Nonvolatile Wiper 0 | 4 |
| Supply current, serial inactive | IDD |  | 2.5 | 5 | µA | Stop condition, SCL = SDA = VIH, Wiper = 0, VDD = 5.5V, HVC/A0 = VIH | 4 |
| VDD start voltage for wiper reset | VBOR |  |  | 1.65 | V | RAM retention voltage (VRAM) < VBOR | 4 |
| Delay after reset exit | TBORD |  | 10 | 20 | µs | VDD > VBOR | 4 |
| Max current through A, W or B | IW |  |  | 2.5 | mA | Terminal W IAW (W = FS) or IBW (W = ZS) | 6 |
| Max RAB current | IAB |  |  | 0.688 | mA | VB = 0V, VA = 5.5V, RAB(MIN) = 8000Ω | 6 |
| Leakage current into A, W or B | IWL |  | 100 |  | nA | MCP44X2 PxB = PxW = VSS | 6 |
| Bandwidth -3 dB, 10 kΩ 8-bit | BW |  | 1 |  | MHz | Code = 80h, load = 30 pF | 7 |
| Capacitance (PA) | CAW |  | 75 |  | pF | f =1 MHz, Code = Full Scale | 9 |
| Capacitance (PW) | CW |  | 120 |  | pF | f =1 MHz, Code = Full Scale | 9 |
| Capacitance (PB) | CBW |  | 75 |  | pF | f =1 MHz, Code = Full Scale | 9 |
| High input threshold, all inputs except SDA/SCL | VIH | 0.45 |  |  | V | 0.45 VDD min, 2.7V ≤ VDD ≤ 5.5V | 10 |
| Low input threshold, all inputs except SDA/SCL | VIL |  |  | 0.2 | V | 0.2VDD max | 10 |
| High voltage input entry voltage | VIHHEN | 9 |  | 12.5 | V | Threshold for WiperLock Technology (Note 6) | 10 |
| High voltage limit | VMAX |  |  | 12.5 | V | Pin can tolerate VMAX or less (Note 6) | 10 |
| SDA output low voltage | VOL |  |  | 0.4 | V | VDD ≥ 2.0V, IOL = 3 mA | 10 |
| Weak pull-up current | IPU |  |  | 1.75 | mA | Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VHVC = 12.5V | 11 |
| Input leakage current | IIL | -1 |  | 1 | µA | VIN = VDD (all pins) and VIN = VSS (all pins except RESET) | 11 |
| EEPROM write cycle time | tWC |  | 3 | 10 | ms |  | 11 |
| RESET pulse width | tRST | 50 |  |  | ns |  | 12 |
| RESET rising edge delay | tRSTD |  |  | 20 | ns | Normal mode (Wiper driving and I2C interface operational) | 12 |
| Absolute max VDD | VDD | -0.6 |  | 7 | V | with respect to VSS | 3 |
| Absolute max HVC/A0, A1, SCL, SDA, WP, RESET |  | -0.6 |  | 12.5 | V | with respect to VSS | 3 |
| Absolute max PxA, PxW, PxB |  | -0.3 |  |  | V | -0.3V to VDD + 0.3V with respect to VSS | 3 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI < 0, VI > VDD, VI > VPP on HV pins | 3 |
| Output clamp current | IOK | -20 |  | 20 | mA | VO < 0 or VO > VDD | 3 |
| Max current into PxA, PxW, PxB |  | -2.5 |  | 2.5 | mA |  | 3 |
| Max current into VDD pin |  |  |  | 100 | mA |  | 3 |
| Max current out of VSS pin |  |  |  | 100 | mA |  | 3 |
| Storage temperature |  | -65 |  | 150 | °C |  | 3 |
| Ambient temperature with power applied |  | -40 |  | 125 | °C |  | 3 |
| Soldering temperature of leads |  |  |  | 300 | °C | 10 seconds | 3 |
| Maximum junction temperature | TJ |  |  | 150 | °C |  | 3 |
| Operating temperature range | TA | -40 |  | 125 | °C | Specified and operating temperature range | 17 |
| Thermal resistance, 14L-TSSOP | θJA |  | 100 |  | °C/W |  | 17 |

## CAD (KiCad official)

- Symbol: `MCP4462-103E`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `mcp4462-103e-etched.step` / `mcp4462-103e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp4462-103e.step` / `mcp4462-103e.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/mcp4462-103e-datasheet.pdf) (100 pp, sha256 `c64d93992e9b7079`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mcp4462-103e-datasheet.pdf)