component
MCP4451T-503E
Public Made by Adomby adom
Microchip Tech Digital Potentiometers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMCP4451T-503E
Microchip Tech · Digital Potentiometers · TSSOP-20
MCP4451T-503E from Microchip Tech, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P3A | passive | Potentiometer 3 terminal A, the full-scale end of resistor network 3, which must stay between VSS and VDD and can carry positive or negative current. |
| 2 | P3W | passive | Potentiometer 3 wiper terminal, which must stay between VSS and VDD and can carry positive or negative current. |
| 3 | P3B | passive | Potentiometer 3 terminal B, the zero-scale end of resistor network 3, which must stay between VSS and VDD and can carry positive or negative current. |
| 4 | HVC/A0 | input | Multiplexed High Voltage Command and I2C Address 0 input, latched at POR/BOR; it is high-voltage tolerant with a Schmitt trigger and has an internal pull-up. |
| 5 | SCL | input | I2C serial clock input, high-voltage tolerant with Schmitt trigger, which accepts only external clock signals since the device is a slave and does not stretch the clock. |
| 6 | SDA | bidirectional | I2C serial data I/O, an open-drain N-channel driver that is high-voltage tolerant with Schmitt trigger input. |
| 7 | VSS | power_in | Device ground reference, to which the VDD input supply is relative. |
| 8 | P1B | passive | Potentiometer 1 terminal B, the zero-scale end of resistor network 1, which must stay between VSS and VDD and can carry positive or negative current. |
| 9 | P1W | passive | Potentiometer 1 wiper terminal, which must stay between VSS and VDD and can carry positive or negative current. |
| 10 | P1A | passive | Potentiometer 1 terminal A, the full-scale end of resistor network 1, which must stay between VSS and VDD and can carry positive or negative current. |
| 11 | P0A | passive | Potentiometer 0 terminal A, the full-scale end of resistor network 0, which must stay between VSS and VDD and can carry positive or negative current. |
| 12 | P0W | passive | Potentiometer 0 wiper terminal, which must stay between VSS and VDD and can carry positive or negative current. |
| 13 | P0B | passive | Potentiometer 0 terminal B, the zero-scale end of resistor network 0, which must stay between VSS and VDD and can carry positive or negative current. |
| 14 | NC | unconnected | No connect pin that is not used; the datasheet says it should be connected to either VDD or VSS. |
| 15 | RESET | input | Hardware reset input, high-voltage tolerant with Schmitt trigger, which forces the device into the POR/BOR state. |
| 16 | A1 | input | I2C Address 1 input, high-voltage tolerant with Schmitt trigger, which should be static and tied high or low. |
| 17 | VDD | power_in | Positive power supply input relative to VSS; electrical performance may not meet data sheet specifications while VDD is below 2.7V. |
| 18 | P2B | passive | Potentiometer 2 terminal B, the zero-scale end of resistor network 2, which must stay between VSS and VDD and can carry positive or negative current. |
| 19 | P2W | passive | Potentiometer 2 wiper terminal, which must stay between VSS and VDD and can carry positive or negative current. |
| 20 | P2A | passive | Potentiometer 2 terminal A, the full-scale end of resistor network 2, which must stay between VSS and VDD and can carry positive or negative current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TSSOP-20 |
| Category | Data Acquisition |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 2.7 | 5.5 | V | 4 | ||
| Supply Voltage (serial interface only) | VDD | 1.8 | 2.7 | V | Serial Interface only. | 4 | |
| Operating Temperature Range | TA | -40 | 125 | °C | 17 | ||
| Ambient Temperature with power applied | TA | -40 | 125 | °C | 3 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 3 | ||
| Voltage on VDD with respect to VSS | VDD | -0.6 | 7 | V | 3 | ||
| Voltage on HVC/A0, A1, SCL, SDA, RESET with respect to VSS | -0.6 | 12.5 | V | 3 | |||
| Voltage on all other pins (PxA, PxW, PxB) with respect to VSS | -0.3 | V | Max VDD + 0.3V | 3 | |||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0, VI > VDD, VI > VPP ON HV pins | 3 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VDD | 3 | |
| Maximum output current sunk by any Output pin | 25 | mA | 3 | ||||
| Maximum output current sourced by any Output pin | 25 | mA | 3 | ||||
| Maximum current into PXA, PXW and PXB pins | -2.5 | 2.5 | mA | 3 | |||
| Maximum current into VDD pin | 100 | mA | 3 | ||||
| Maximum current out of VSS pin | 100 | mA | 3 | ||||
| Maximum Junction Temperature | TJ | 150 | °C | 3 | |||
| ESD protection on all pins (HBM) | 4 | kV | HBM | 3 | |||
| Supply Current, serial interface active at 3.4 MHz | IDD | 600 | µA | Serial Interface Active, HVC/A0 = VIH (or VIL), Write all 0's to volatile Wiper 0, VDD = 5.5V, FSCL @ 3.4 MHz | 4 | ||
| Supply Current, serial interface active at 100 kHz | IDD | 250 | µA | Serial Interface Active, HVC/A0 = VIH (or VIL), Write all 0's to volatile Wiper 0, VDD = 5.5V, FSCL @ 100 kHz | 4 | ||
| Supply Current, serial interface inactive | IDD | 2.5 | 5 | µA | Serial Interface Inactive, (Stop condition, SCL = SDA = VIH), Wiper = 0, VDD = 5.5V, HVC/A0 = VIH | 4 | |
| VDD Start Voltage to ensure Wiper Reset | VBOR | 1.65 | V | RAM retention voltage (VRAM) < VBOR | 4 | ||
| Delay after device exits the Reset state | TBORD | 10 | 20 | µs | VDD > VBOR | 4 | |
| HVC/A0, SDA, SCL, A1, RESET pin voltage range | VHV | 12.5 | V | VDD >= 4.5V | 4 | ||
| Nominal Resistance RAB (-503 device) | RAB | 40 | 50 | 60 | k | -503 devices (Note 1) | 5 |
| Resistance tolerance (-503 device) | RAB | -20 | 20 | % | Resistance (± 20%), -503 devices | 5 | |
| Nominal Resistance Match | 0.2 | 1 | % | 50 k | 5 | ||
| Nominal Resistance Match, RBW worst case from mean | 0.25 | 1.25 | % | 50 k | 5 | ||
| Wiper Resistance, VDD = 5.5 V | RW | 75 | 160 | Ω | VDD = 5.5 V, IW = 2.0 mA, code = 00h | 5 | |
| Wiper Resistance, VDD = 2.7 V | RW | 75 | 300 | Ω | VDD = 2.7 V, IW = 2.0 mA, code = 00h | 5 | |
| Full Scale Error (8-bit, 50 k) | VWFSE | -0.8 | -0.1 | LSb | 50 k 8-bit 3.0V ≤ VDD ≤ 5.5V | 7 | |
| Zero Scale Error (8-bit, 50 k) | VWZSE | 0.1 | 0.8 | LSb | 50 k 8-bit 3.0V ≤ VDD ≤ 5.5V | 7 | |
| Potentiometer Integral Non-linearity (8-bit) | INL | -1 | 0.5 | 1 | LSb | 8-bit 3.0V ≤ VDD ≤ 5.5V, MCP44X1 devices only (Note 2) | 7 |
| Potentiometer Differential Non-linearity (8-bit) | DNL | -0.5 | 0.25 | 0.5 | LSb | 8-bit 3.0V ≤ VDD ≤ 5.5V, MCP44X1 devices only (Note 2) | 7 |
| Rheostat Integral Non-linearity (50 k, 5.5V) | R-INL | -1.5 | 0.5 | 1.5 | LSb | 50 k 8-bit 5.5V, IW = 90 µA | 8 |
| Rheostat Integral Non-linearity (50 k, 3.0V) | R-INL | -2 | 1 | 2 | LSb | 50 k 8-bit 3.0V, IW = 48 µA (Note 7) | 8 |
| Rheostat Differential Non-linearity (50 k, 5.5V) | R-DNL | -0.5 | 0.25 | 0.5 | LSb | 50 k 8-bit 5.5V, IW = 90 µA | 9 |
| Rheostat Differential Non-linearity (50 k, 3.0V) | R-DNL | -0.5 | 0.25 | 0.5 | LSb | 50 k 8-bit 3.0V, IW = 48 µA (Note 7) | 9 |
| Schmitt Trigger High Input Threshold, all inputs except SDA and SCL | VIH | 0.45 | VDD | 2.7V ≤ VDD ≤ 5.5V | 10 | ||
| Schmitt Trigger High Input Threshold, SDA and SCL | VIH | 0.7 | VDD | SDA and SCL, 100 kHz, 400 kHz, 1.7 MHz, 3.4 MHz | 10 | ||
| Schmitt Trigger Low Input Threshold, all inputs except SDA and SCL | VIL | 0.2 | VDD | All inputs except SDA and SCL | 10 | ||
| Schmitt Trigger Low Input Threshold, SDA and SCL | VIL | -0.5 | 0.3 | VDD | SDA and SCL, 100 kHz, 400 kHz, 1.7 MHz, 3.4 MHz | 10 | |
| Output Low Voltage (SDA), VDD < 2.0V | VOL | 0.2 | VDD | VDD < 2.0V, IOL = 1 mA | 10 | ||
| Output Low Voltage (SDA), VDD ≥ 2.0V | VOL | 0.4 | V | VDD ≥ 2.0V, IOL = 3 mA | 10 | ||
| High Voltage Input Entry Voltage | VIHHEN | 9 | 12.5 | V | Threshold for WiperLock Technology (Note 6) | 10 | |
| High Voltage Limit | VMAX | 12.5 | V | Pin can tolerate VMAX or less (Note 6) | 10 | ||
| Weak Pull-up Current, internal VDD pull-up | IPU | 1.75 | mA | Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VHVC = 12.5V | 11 | ||
| Input Leakage Current | IIL | -1 | 1 | µA | VIN = VDD (all pins) and VIN = VSS (all pins except RESET) | 11 | |
| RESET pulse width | tRST | 50 | ns | 12 | |||
| RESET rising edge, normal mode | tRSTD | 20 | ns | Wiper driving and I2C interface operational | 12 | ||
| Nominal Resistance Tempco | RAB/T | 50 | ppm/°C | TA = -20°C to +70°C | 5 | ||
| Nominal Resistance Tempco | RAB/T | 100 | ppm/°C | TA = -40°C to +85°C | 5 | ||
| Nominal Resistance Tempco | RAB/T | 150 | ppm/°C | TA = -40°C to +125°C | 5 | ||
| Ratiometric Tempco | VWB/T | 15 | ppm/°C | Code = Midscale (80h or 40h) | 5 | ||
| Bandwidth -3 dB, 50 k, 8-bit | BW | 200 | kHz | 50 k 8-bit Code = 80h, load = 30 pF | 7 | ||
| Pin Capacitance | CIN, COUT | 10 | pF | fC = 20 MHz | 11 | ||
| HVC Pull-up / Pull-down Resistance | RHVC | 16 | k | VDD = 5.5V, VHVC = 3V | 11 | ||
| RESET Pull-up Resistance | RRESET | 16 | k | VDD = 5.5V, VRESET = 0V | 11 | ||
| Thermal Resistance, 20L-TSSOP | θJA | 90 | °C/W | 17 |
CAD (KiCad official)
- Symbol:
MCP4451T-503E - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
mcp4451t-503e-etched.step/mcp4451t-503e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4451t-503e.step/mcp4451t-503e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (94 pp, sha256
3e69021e45ebc441, retrieved 2026-10-16, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).