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MCP4451-104E

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Microchip Tech Digital Potentiometers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MCP4451-104E

Microchip Tech · Digital Potentiometers · TSSOP-20

MCP4451-104E from Microchip Tech, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P3A passive Potentiometer 3 terminal A, the fixed full-scale connection, which must be held between VSS and VDD.
2 P3W passive Potentiometer 3 wiper terminal, which must be held between VSS and VDD.
3 P3B passive Potentiometer 3 terminal B, the fixed zero-scale connection, which must be held between VSS and VDD.
4 HVC/A0 input High-voltage-tolerant Schmitt-trigger input with a smart pull-up that serves as I2C address bit 0 (latched at POR/BOR) and as the High Voltage Command pin when driven to VIHH.
5 SCL input High-voltage-tolerant Schmitt-trigger I2C clock input from the host, supporting clock rates up to 100 kHz, 400 kHz and 3.4 MHz.
6 SDA bidirectional High-voltage-tolerant I2C serial data pin with an open-drain N-channel output driver.
7 VSS power_in Ground reference for the device.
8 P1B passive Potentiometer 1 terminal B, the fixed zero-scale connection, which must be held between VSS and VDD.
9 P1W passive Potentiometer 1 wiper terminal, which must be held between VSS and VDD.
10 P1A passive Potentiometer 1 terminal A, the fixed full-scale connection, which must be held between VSS and VDD.
11 P0A passive Potentiometer 0 terminal A, the fixed full-scale connection, which must be held between VSS and VDD.
12 P0W passive Potentiometer 0 wiper terminal, which must be held between VSS and VDD.
13 P0B passive Potentiometer 0 terminal B, the fixed zero-scale connection, which must be held between VSS and VDD.
14 NC unconnected No-connect pin that is not used internally.
15 RESET input High-voltage-tolerant Schmitt-trigger hardware reset input with weak pull-up that forces the device into the POR/BOR state.
16 A1 input High-voltage-tolerant Schmitt-trigger I2C address bit 1 input with smart pull-up, which should be tied static high or low.
17 VDD power_in Positive power supply input relative to VSS, with 1.8V to 5.5V device operation and 2.7V to 5.5V for specified characteristics.
18 P2B passive Potentiometer 2 terminal B, the fixed zero-scale connection, which must be held between VSS and VDD.
19 P2W passive Potentiometer 2 wiper terminal, which must be held between VSS and VDD.
20 P2A passive Potentiometer 2 terminal A, the fixed full-scale connection, which must be held between VSS and VDD.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TSSOP-20
Category ADC/DAC/Data Conversion
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Nominal resistance RAB (-104) RAB 80 100 120 kΩ -104 devices (Note 1), ±20% 5
Supply Voltage VDD 2.7 5.5 V 4
Supply Voltage (serial interface only) VDD 1.8 2.7 V Serial Interface only 4
Wiper resistance RW 75 160 Ω VDD = 5.5 V, IW = 2.0 mA, code = 00h 5
Wiper resistance RW 75 300 Ω VDD = 2.7 V, IW = 2.0 mA, code = 00h 5
Supply current, interface active 3.4 MHz IDD 600 µA Serial Interface Active, VDD = 5.5V, FSCL @ 3.4 MHz 4
Supply current, interface active 100 kHz IDD 250 µA Serial Interface Active, VDD = 5.5V, FSCL @ 100 kHz 4
Supply current, interface inactive IDD 2.5 5 µA Stop condition, SCL = SDA = VIH, Wiper = 0, VDD = 5.5V, HVC/A0 = VIH 4
VDD start voltage for wiper reset VBOR 1.65 V RAM retention voltage (VRAM) < VBOR 4
Delay after reset exit TBORD 10 20 µs 4
Nominal resistance match /RABWC - RABMEAN//RABMEAN 0.2 1 % 100 k, MCP44X1 devices only 5
RBW match /RBWWC - RBWMEAN//RBWMEAN 0.25 1.25 % 100 k, Code = Full Scale 5
Full scale error 8-bit VWFSE -0.5 -0.1 LSb 100 k 8-bit 3.0V ≤ VDD ≤ 5.5V 7
Zero scale error 8-bit VWZSE 0.1 0.5 LSb 100 k 8-bit 3.0V ≤ VDD ≤ 5.5V 7
Potentiometer INL 8-bit INL -1 0.5 1 LSb 8-bit 3.0V ≤ VDD ≤ 5.5V, MCP44X1 only (Note 2) 7
Potentiometer DNL 8-bit DNL -0.5 0.25 0.5 LSb 8-bit 3.0V ≤ VDD ≤ 5.5V, MCP44X1 only (Note 2) 7
Rheostat INL 100k 8-bit R-INL -1 0.5 1 LSb 100 k 8-bit 5.5V, IW = 45 µA 8
Rheostat INL 100k 8-bit R-INL -1.5 0.25 1.5 LSb 100 k 8-bit 3.0V, IW = 24 µA (Note 7) 8
Rheostat DNL 100k 8-bit R-DNL -0.5 0.25 0.5 LSb 100 k 8-bit 5.5V, IW = 45 µA 9
Power supply sensitivity 8-bit PSS 0.0015 0.0035 %/% VDD = 2.7V to 5.5V, VA = 2.7V, Code = 80h 11
Input leakage current IIL -1 1 µA VIN = VDD (all pins) and VIN = VSS (all pins except RESET) 11
Schmitt trigger high threshold (non SDA/SCL) VIH 0.45 V 0.45 VDD min, 2.7V ≤ VDD ≤ 5.5V, all inputs except SDA and SCL 10
Schmitt trigger low threshold (non SDA/SCL) VIL 0.2 V 0.2 VDD max, all inputs except SDA and SCL 10
Output low voltage SDA VOL 0.4 V VDD ≥ 2.0V, IOL = 3 mA 10
Maximum current through A, W or B IW 2.5 mA Terminal A IAW, W = Full Scale 6
Maximum RAB current IAB 0.069 mA VB = 0V, VA = 5.5V, RAB(MIN) = 80000Ω 6
RESET pulse width tRST 50 ns 12
Nominal resistance tempco ΔRAB/ΔT 50 ppm/°C TA = -20°C to +70°C 5
Nominal resistance tempco ΔRAB/ΔT 100 ppm/°C TA = -40°C to +85°C 5
Nominal resistance tempco ΔRAB/ΔT 150 ppm/°C TA = -40°C to +125°C 5
Ratiometric tempco ΔVWB/ΔT 15 ppm/°C Code = Midscale (80h or 40h) 5
Bandwidth -3 dB BW 100 kHz 100 k 8-bit Code = 80h, load 30 pF 7
Operating temperature range TA -40 125 °C 17
VDD voltage VDD -0.6 7 V with respect to VSS 3
Voltage on HVC/A0, A1, SCL, SDA, RESET -0.6 12.5 V with respect to VSS 3
Voltage on PxA, PxW, PxB -0.3 V -0.3V to VDD + 0.3V, with respect to VSS 3
Maximum current into PxA, PxW, PxB -2.5 2.5 mA 3
Storage temperature -65 150 °C 3
Maximum junction temperature TJ 150 °C 3
Thermal resistance 20L-TSSOP θJA 90 °C/W 17

CAD (KiCad official)

  • Symbol: MCP4451-104E
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: mcp4451-104e-etched.step / mcp4451-104e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp4451-104e.step / mcp4451-104e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (94 pp, sha256 3e69021e45ebc441, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF