component
MCP4451-103E
Public Made by Adomby adom
Microchip Tech Digital Potentiometers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMCP4451-103E
Microchip Tech · Digital Potentiometers · TSSOP-20
MCP4451-103E from Microchip Tech, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P3A | passive | Potentiometer 3 Terminal A, the fixed full-scale connection (wiper 0x100 on 8-bit devices), voltage must be between VSS and VDD. |
| 2 | P3W | passive | Potentiometer 3 wiper terminal, supports positive and negative current, voltage must be between VSS and VDD. |
| 3 | P3B | passive | Potentiometer 3 Terminal B, the fixed zero-scale connection (wiper 0x00), voltage must be between VSS and VDD. |
| 4 | HVC/A0 | input | High Voltage Command / I2C Address 0 input (high-voltage tolerant with Schmitt trigger, smart weak pull-up); A0 is latched at POR/BOR and a normal vs high-voltage command is selected by VIHH. |
| 5 | SCL | input | I2C clock input from the host controller (high-voltage tolerant with Schmitt trigger, no weak pull-up); the device is a slave and accepts only external clocks. |
| 6 | SDA | bidirectional | I2C serial data I/O with open-drain N-channel output (high-voltage tolerant with Schmitt trigger, no weak pull-up). |
| 7 | VSS | power_in | Ground reference for the device. |
| 8 | P1B | passive | Potentiometer 1 Terminal B, the fixed zero-scale connection, voltage must be between VSS and VDD. |
| 9 | P1W | passive | Potentiometer 1 wiper terminal, voltage must be between VSS and VDD. |
| 10 | P1A | passive | Potentiometer 1 Terminal A, the fixed full-scale connection, voltage must be between VSS and VDD. |
| 11 | P0A | passive | Potentiometer 0 Terminal A, the fixed full-scale connection, voltage must be between VSS and VDD. |
| 12 | P0W | passive | Potentiometer 0 wiper terminal, voltage must be between VSS and VDD. |
| 13 | P0B | passive | Potentiometer 0 Terminal B, the fixed zero-scale connection, voltage must be between VSS and VDD. |
| 14 | NC | unconnected | No connect; datasheet states the pin is not used and should be connected to VDD or VSS. |
| 15 | RESET | input | Hardware reset input (high-voltage tolerant with Schmitt trigger, weak pull-up) that forces the device into the POR/BOR state. |
| 16 | A1 | input | I2C Address 1 input (high-voltage tolerant with Schmitt trigger, smart pull-up) that with A0 allows up to 4 devices on one bus; should be tied static high or low. |
| 17 | VDD | power_in | Positive power supply input relative to VSS; device operates 1.8V to 5.5V with specifications guaranteed 2.7V to 5.5V. |
| 18 | P2B | passive | Potentiometer 2 Terminal B, the fixed zero-scale connection, voltage must be between VSS and VDD. |
| 19 | P2W | passive | Potentiometer 2 wiper terminal, voltage must be between VSS and VDD. |
| 20 | P2A | passive | Potentiometer 2 Terminal A, the fixed full-scale connection, voltage must be between VSS and VDD. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TSSOP-20 |
| Category | Data Converters |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal resistance RAB tolerance | RAB | -20 | 20 | % | -103 devices (Note 1) | 5 | |
| Nominal resistance (10k) | RAB | 8 | 10 | 12 | kΩ | -103 devices (Note 1) | 5 |
| Supply Voltage | VDD | 2.7 | 5.5 | V | Device characteristics specified | 4 | |
| Supply Voltage (serial interface only) | VDD | 1.8 | 2.7 | V | Serial Interface only | 4 | |
| Operating temperature | TA | -40 | 125 | °C | Operating Temperature Range | 17 | |
| Specified temperature range | TA | -40 | 125 | °C | 17 | ||
| HV pin voltage range | VHV | 12.5 | V | VDD ≥ 4.5V; VSS to 12.5V; VDD < 4.5V: VSS to VDD + 8.0V | 4 | ||
| Resistor terminal input voltage range | VA,VW,VB | 0 | V | VSS to VDD (Note 5, Note 6) | 6 | ||
| Voltage on VDD wrt VSS | VDD | -0.6 | 7 | V | 3 | ||
| Voltage on HVC/A0, A1, SCL, SDA, RESET wrt VSS | -0.6 | 12.5 | V | 3 | |||
| Voltage on PxA, PxW, PxB wrt VSS | -0.3 | V | -0.3V to VDD + 0.3V | 3 | |||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0, VI > VDD, VI > VPP on HV pins | 3 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VDD | 3 | |
| Max output current sunk by any output pin | 25 | mA | 3 | ||||
| Max output current sourced by any output pin | 25 | mA | 3 | ||||
| Max current out of VSS pin | 100 | mA | 3 | ||||
| Max current into VDD pin | 100 | mA | 3 | ||||
| Max current into PxA, PxW, PxB pins | -2.5 | 2.5 | mA | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Ambient temperature with power applied | -40 | 125 | °C | 3 | |||
| Soldering temperature of leads | 300 | °C | 10 seconds | 3 | |||
| ESD protection (HBM) | 4 | kV | all pins, HBM (MM 300V) | 3 | |||
| Maximum junction temperature | TJ | 150 | °C | 3 | |||
| Thermal resistance, 20L-TSSOP | θJA | 90 | °C/W | 17 | |||
| VDD start voltage for wiper reset | VBOR | 1.65 | V | RAM retention voltage (VRAM) < VBOR | 4 | ||
| Delay after exit from Reset | TBORD | 10 | 20 | µs | VDD > VBOR | 4 | |
| Supply current, active 3.4 MHz | IDD | 600 | µA | Serial interface active, HVC/A0 = VIH (or VIL), write all 0's to volatile Wiper 0, VDD = 5.5V, FSCL @ 3.4 MHz | 4 | ||
| Supply current, active 100 kHz | IDD | 250 | µA | Serial interface active, HVC/A0 = VIH (or VIL), write all 0's to volatile Wiper 0, VDD = 5.5V, FSCL @ 100 kHz | 4 | ||
| Supply current, serial interface inactive | IDD | 2.5 | 5 | µA | Stop condition, SCL = SDA = VIH, Wiper = 0, VDD = 5.5V, HVC/A0 = VIH | 4 | |
| Wiper resistance (5.5V) | RW | 75 | 160 | Ω | VDD = 5.5 V, IW = 2.0 mA, code = 00h | 5 | |
| Wiper resistance (2.7V) | RW | 75 | 300 | Ω | VDD = 2.7 V, IW = 2.0 mA, code = 00h | 5 | |
| Nominal resistance tempco | ΔRAB/ΔT | 50 | ppm/°C | TA = -20°C to +70°C | 5 | ||
| Nominal resistance tempco | ΔRAB/ΔT | 100 | ppm/°C | TA = -40°C to +85°C | 5 | ||
| Nominal resistance tempco | ΔRAB/ΔT | 150 | ppm/°C | TA = -40°C to +125°C | 5 | ||
| Ratiometric tempco | ΔVWB/ΔT | 15 | ppm/°C | Code = Midscale (80h or 40h) | 5 | ||
| Nominal resistance match (RAB) | 0.2 | 1.25 | % | 10 k, MCP44X1 devices only | 5 | ||
| Nominal resistance match (RBW) | 0.25 | 1.5 | % | 10 k, Code = Full Scale | 5 | ||
| Maximum current through A, W or B | IW | 2.5 | mA | Terminal A IAW, W = Full Scale (FS) | 6 | ||
| Maximum RAB current | IAB | 0.688 | mA | VB = 0V, VA = 5.5V, RAB(MIN) = 8000Ω | 6 | ||
| Leakage current into A, W or B | IWL | 100 | nA | MCP44X1 PxA = PxW = PxB = VSS | 6 | ||
| Full scale error | VWFSE | -3.5 | -0.1 | LSb | 10 k 8-bit 3.0V ≤ VDD ≤ 5.5V | 7 | |
| Zero scale error | VWZSE | 0.1 | 3.5 | LSb | 10 k 8-bit 3.0V ≤ VDD ≤ 5.5V | 7 | |
| Potentiometer INL | INL | -1 | 0.5 | 1 | LSb | 8-bit 3.0V ≤ VDD ≤ 5.5V, MCP44X1 only (Note 2) | 7 |
| Potentiometer DNL | DNL | -0.5 | 0.25 | 0.5 | LSb | 8-bit 3.0V ≤ VDD ≤ 5.5V, MCP44X1 only (Note 2) | 7 |
| Bandwidth -3 dB | BW | 1 | MHz | 10 k 8-bit Code = 80h, load = 30 pF | 7 | ||
| Rheostat INL | R-INL | -1.5 | 0.5 | 1.5 | LSb | 10 k 8-bit 5.5V, IW = 450 µA | 8 |
| Rheostat INL | R-INL | -5.5 | 2.5 | 5.5 | LSb | 10 k 8-bit 3.0V, IW = 240 µA (Note 7) | 8 |
| Rheostat DNL | R-DNL | -0.5 | 0.25 | 0.5 | LSb | 10 k 8-bit 5.5V, IW = 450 µA | 9 |
| Rheostat DNL | R-DNL | -1 | 0.25 | 1 | LSb | 10 k 8-bit 3.0V, IW = 240 µA (Note 7) | 9 |
| Schmitt trigger high input threshold | VIH | 0.45 | V | All inputs except SDA and SCL, 2.7V ≤ VDD ≤ 5.5V (min 0.45 VDD) | 10 | ||
| Schmitt trigger low input threshold | VIL | 0.2 | V | All inputs except SDA and SCL (max 0.2VDD) | 10 | ||
| High voltage input entry voltage | VIHHEN | 9 | 12.5 | V | Threshold for WiperLock Technology (Note 6) | 10 | |
| High voltage limit | VMAX | 12.5 | V | Pin can tolerate VMAX or less (Note 6) | 10 | ||
| Output low voltage (SDA) | VOL | 0 | 0.4 | V | VDD ≥ 2.0V, IOL = 3 mA | 10 | |
| Input leakage current | IIL | -1 | 1 | µA | VIN = VDD (all pins) and VIN = VSS (all pins except RESET) | 11 | |
| Power supply sensitivity | PSS | 0.0015 | 0.0035 | %/% | 8-bit VDD = 2.7V to 5.5V, VA = 2.7V, Code = 80h | 11 | |
| RESET pulse width | tRST | 50 | ns | 12 | |||
| RESET rising edge normal mode delay | tRSTD | 20 | ns | 12 | |||
| Pin capacitance | CIN, COUT | 10 | pF | fC = 20 MHz | 11 | ||
| Capacitance (PW) | CW | 120 | pF | f = 1 MHz, Code = Full Scale | 11 |
CAD (KiCad official)
- Symbol:
MCP4451-103E - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
mcp4451-103e-etched.step/mcp4451-103e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4451-103e.step/mcp4451-103e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (94 pp, sha256
3e69021e45ebc441, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).