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MCP4441-502E
Public Made by Adomby adom
Microchip Tech Digital Potentiometers, QFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MCP4441-502E
Microchip Tech · Digital Potentiometers · QFN-20-EP(4x4)
MCP4441-502E from Microchip Tech, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P3B | passive | Terminal B of potentiometer 3, the fixed zero-scale connection (wiper code 0x00), with a voltage that must stay between VSS and VDD. |
| 2 | HVC/A0 | input | I2C Address 0 input, latched at POR/BOR, that also serves as the High Voltage Command pin when driven to VIHH. |
| 3 | SCL | input | I2C serial clock input, a high-voltage tolerant Schmitt-trigger input that accepts only external clock signals since the device is a slave. |
| 4 | SDA | bidirectional | I2C serial data I/O implemented as an open-drain N-channel driver. |
| 5 | VSS | power_in | Device ground reference. |
| 6 | P1B | passive | Terminal B of potentiometer 1, the fixed zero-scale connection (wiper code 0x00), with a voltage that must stay between VSS and VDD. |
| 7 | P1W | passive | Wiper terminal of potentiometer 1, which may carry positive or negative current with its voltage kept between VSS and VDD. |
| 8 | P1A | passive | Terminal A of potentiometer 1 (available on MCP44X1 devices), the fixed full-scale connection with its voltage kept between VSS and VDD. |
| 9 | P0A | passive | Terminal A of potentiometer 0 (available on MCP44X1 devices), the fixed full-scale connection with its voltage kept between VSS and VDD. |
| 10 | P0W | passive | Wiper terminal of potentiometer 0, which may carry positive or negative current with its voltage kept between VSS and VDD. |
| 11 | P0B | passive | Terminal B of potentiometer 0, the fixed zero-scale connection (wiper code 0x00), with a voltage that must stay between VSS and VDD. |
| 12 | WP | input | Hardware EEPROM Write Protect input that forces the nonvolatile memory to be write protected. |
| 13 | RESET | input | Hardware reset input, a high-voltage tolerant Schmitt-trigger input that forces the device into the POR/BOR state. |
| 14 | A1 | input | I2C Address 1 input, a high-voltage tolerant Schmitt-trigger input that together with A0 sets the device address. |
| 15 | VDD | power_in | Positive power supply input relative to VSS, where electrical performance may not meet datasheet specifications while VDD is below 2.7V. |
| 16 | P2B | passive | Terminal B of potentiometer 2, the fixed zero-scale connection (wiper code 0x00), with a voltage that must stay between VSS and VDD. |
| 17 | P2W | passive | Wiper terminal of potentiometer 2, which may carry positive or negative current with its voltage kept between VSS and VDD. |
| 18 | P2A | passive | Terminal A of potentiometer 2 (available on MCP44X1 devices), the fixed full-scale connection with its voltage kept between VSS and VDD. |
| 19 | P3A | passive | Terminal A of potentiometer 3 (available on MCP44X1 devices), the fixed full-scale connection with its voltage kept between VSS and VDD. |
| 20 | P3W | passive | Wiper terminal of potentiometer 3, which may carry positive or negative current with its voltage kept between VSS and VDD. |
| 21 | EP | passive | Exposed pad conductively connected to the die substrate, which should be tied to the VSS potential or left unconnected and can serve as a heat sink. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-20-EP(4x4) |
| Category | ADC/DAC/Data Conversion |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| RAB resistance (-502, 5 kΩ) | RAB | 4 | 5 | 6 | kΩ | -502 devices (Note 1) | 5 |
| RAB resistance tolerance | -20 | 20 | % | Resistance (± 20%) as printed for RAB | 5 | ||
| Nominal resistance match (5 kΩ, MCP44X1) | (/RABWC - RABMEAN/)/RABMEAN | 0.2 | 1.5 | % | 5 kΩ MCP44X1 devices only | 5 | |
| Ratiometric resistance match (5 kΩ) | (/RBWWC - RBWMEAN/)/RBWMEAN | 0.25 | 1.75 | % | 5 kΩ, Code = Full Scale | 5 | |
| Wiper resistance | RW | 75 | 160 | Ω | VDD = 5.5 V, IW = 2.0 mA, code = 00h | 5 | |
| Wiper resistance | RW | 75 | 300 | Ω | VDD = 2.7 V, IW = 2.0 mA, code = 00h | 5 | |
| VDD supply voltage | VDD | 2.7 | 5.5 | V | 4 | ||
| VDD supply voltage (device operation) | VDD | 1.8 | 2.7 | V | Serial Interface only. | 4 | |
| Voltage range on HVC/A0, SDA, SCL, A1, WP, RESET | VHV | 12.5 | V | VDD ≥ 4.5V | 4 | ||
| VDD start voltage to ensure wiper reset (POR/BOR) | VBOR | 1.65 | V | RAM retention voltage (VRAM) < VBOR | 4 | ||
| Delay after device exits reset state | TBORD | 10 | 20 | µs | VDD > VBOR | 4 | |
| Supply current (serial interface active) | IDD | 600 | µA | Serial Interface Active, HVC/A0 = VIH (or VIL) (Note 11); write all 0's to volatile Wiper 0; VDD = 5.5V, FSCL @ 3.4 MHz | 4 | ||
| Supply current (serial interface active) | 250 | µA | Serial Interface Active, HVC/A0 = VIH (or VIL) (Note 11); write all 0's to volatile Wiper 0; VDD = 5.5V, FSCL @ 100 kHz | 4 | |||
| EE write current (write cycle, nonvolatile device) | 575 | µA | VDD = 5.5V, FSCL = 400 kHz, write all 0's to nonvolatile Wiper 0, SCL = VIL or VIH | 4 | |||
| Serial interface inactive current | 2.5 | 5 | µA | Stop condition, SCL = SDA = VIH, Wiper = 0; VDD = 5.5V, HVC/A0 = VIH | 4 | ||
| Maximum current through terminal A | IW | 2.5 | mA | Terminal A IAW, W = Full Scale (FS) | 6 | ||
| Maximum current through terminal B | 2.5 | mA | Terminal B IBW, W = Zero Scale (ZS) | 6 | |||
| Maximum current through terminal W | 2.5 | mA | Terminal W IAW (W = FS) or IBW (W = ZS) | 6 | |||
| Maximum RAB current (5 kΩ device) | IAB | 1.38 | mA | VB = 0V, VA = 5.5V, RAB(MIN) = 4000Ω | 6 | ||
| Full scale error (MCP44X1), 7-bit | VWFSE | -4 | -0.1 | LSb | 5 kΩ, 7-bit code = 80h, 3.0V ≤ VDD ≤ 5.5V | 7 | |
| Zero scale error (MCP44X1), 7-bit | VWZSE | 0.1 | 3 | LSb | 5 kΩ, 7-bit code = 00h, 3.0V ≤ VDD ≤ 5.5V | 7 | |
| Potentiometer integral non-linearity, 7-bit | INL | -0.5 | 0.25 | 0.5 | LSb | 7-bit | 7 |
| Potentiometer differential non-linearity, 7-bit | DNL | -0.25 | 0.125 | 0.25 | LSb | 7-bit | 7 |
| Rheostat integral non-linearity (MCP44X1, Note 8) | R-INL | -1.125 | 0.5 | 1.125 | LSb | 5 kΩ 7-bit 5.5V, IW = 900 µA | 8 |
| Rheostat integral non-linearity (MCP44X1, Note 8) | R-INL | -6 | 4.5 | 6 | LSb | 5 kΩ 7-bit 3.0V, IW = 480 µA (Note 7) | 8 |
| Rheostat differential non-linearity (MCP44X1, Note 8) | R-DNL | -0.375 | 0.25 | 0.375 | LSb | 5 kΩ 7-bit 5.5V, IW = 900 µA | 9 |
| Rheostat differential non-linearity (MCP44X1, Note 8) | R-DNL | -0.75 | 0.5 | 0.75 | LSb | 5 kΩ 7-bit 3.0V, IW = 480 µA (Note 7) | 9 |
| WiperLock high-voltage input entry voltage | VIHHEN | 9 | 12.5 | V | Threshold for WiperLock Technology | 10 | |
| High voltage limit | VMAX | 12.5 | V | Pin can tolerate VMAX or less. | 10 | ||
| Output low voltage (SDA) | VOL | 0.4 | V | VDD ≥ 2.0V, IOL = 3 mA | 10 | ||
| Weak pull-up current | IPU | 1.75 | mA | Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VHVC = 12.5V | 11 | ||
| Input leakage current | IIL | -1 | 1 | µA | VIN = VDD (all pins) and VIN = VSS (all pins except RESET) | 11 | |
| EEPROM programming write cycle time | tWC | 3 | 10 | ms | 11 | ||
| Power supply sensitivity (7-bit) | PSS | 0.0015 | 0.0035 | %/% | 7-bit VDD = 2.7V to 5.5V, VA = 2.7V, Code = 40h | 11 | |
| RESET pulse width | tRST | 50 | ns | 12 | |||
| RESET rising edge delay (normal mode) | tRSTD | 20 | ns | RESET rising edge normal mode (Wiper driving and I2C interface operational) | 12 | ||
| HVC to SCL setup time | THVCSU | 25 | uS | High Voltage Commands | 13 | ||
| SCL to HVC hold time | THVCHD | 25 | uS | High Voltage Commands | 13 | ||
| Voltage on VDD with respect to VSS | -0.6 | 7 | V | 3 | |||
| Voltage on HVC/A0, A1, SCL, SDA, WP, RESET with respect to VSS | -0.6 | 12.5 | V | 3 | |||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0, VI > VDD, VI > VPP on HV pins | 3 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VDD | 3 | |
| Maximum output current sunk by any output pin | 25 | mA | 3 | ||||
| Maximum output current sourced by any output pin | 25 | mA | 3 | ||||
| Maximum current out of VSS pin | 100 | mA | 3 | ||||
| Maximum current into VDD pin | 100 | mA | 3 | ||||
| Maximum current into PxA, PxW, PxB pins | -2.5 | 2.5 | mA | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Ambient temperature with power applied | -40 | 125 | °C | 3 | |||
| Maximum junction temperature | TJ | 150 | °C | 3 | |||
| Soldering temperature of leads | 300 | °C | 10 seconds | 3 | |||
| ESD protection, HBM | 4 | kV | HBM | 3 | |||
| ESD protection, MM | 300 | V | MM | 3 | |||
| Nominal resistance tempco | ΔRAB/ΔT | 50 | ppm/°C | TA = -20°C to +70°C | 5 | ||
| Nominal resistance tempco | ΔRAB/ΔT | 100 | ppm/°C | TA = -40°C to +85°C | 5 | ||
| Nominal resistance tempco | ΔRAB/ΔT | 150 | ppm/°C | TA = -40°C to +125°C | 5 | ||
| Ratiometric tempco | ΔVWB/ΔT | 15 | ppm/°C | Code = Midscale (80h or 40h) | 5 | ||
| Thermal resistance, 20L-QFN | θJA | 43 | °C/W | 17 | |||
| Operating temperature range | TA | -40 | 125 | °C | Extended | 17 |
CAD (KiCad official)
- Symbol:
MCP4441-502E - Footprint:
Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm - 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
mcp4441-502e-etched.step/mcp4441-502e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4441-502e.step/mcp4441-502e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (100 pp, sha256
c64d93992e9b7079, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).