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MCP4351-104E

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Microchip Tech Digital Potentiometers, QFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionmcp4351-104efactory-2.0.0extractor-text

Verified MCP4351-104E

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 21 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: MCP4351-104E · QFN-20-EP(4x4) · 21 pins
  • ✓copper: 21 copper pads, none touching another net
  • ✓datasheet: all 21 pin names found in the 88-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-v5x3a98r/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 21 pins = 21 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 21 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ mcp4351-104e.kicad_sym✓ mcp4351-104e.kicad_mod✓ mcp4351-104e.step
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Ray Publish 0.1.0 bd2f53d 7d ago

MCP4351-104E

Microchip Tech · Digital Potentiometers · QFN-20-EP(4x4)

MCP4351-104E from Microchip Tech, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P3B passive Potentiometer 3 terminal B, the zero-scale (wiper 0x00) connection; voltage must be between VSS and VDD and it carries current of either polarity.
2 CS input SPI chip select input, high-voltage tolerant with Schmitt trigger; VIL enables serial commands and VIHH enables high-voltage serial commands.
3 SCK input SPI serial clock input (input only, slave device), high-voltage tolerant with Schmitt trigger.
4 SDI input SPI serial data input, connected to the host controller's SDO pin; high-voltage tolerant with Schmitt trigger.
5 VSS power_in Device ground reference.
6 P1B passive Potentiometer 1 terminal B, the zero-scale connection; voltage must be between VSS and VDD.
7 P1W passive Potentiometer 1 wiper terminal; voltage must be between VSS and VDD.
8 P1A passive Potentiometer 1 terminal A, the full-scale connection (0x100 for 8-bit); voltage must be between VSS and VDD.
9 P0A passive Potentiometer 0 terminal A, the full-scale connection (0x100 for 8-bit); voltage must be between VSS and VDD.
10 P0W passive Potentiometer 0 wiper terminal; voltage must be between VSS and VDD.
11 P0B passive Potentiometer 0 terminal B, the zero-scale connection; voltage must be between VSS and VDD.
12 NC unconnected No connect; the pin is not used.
13 RESET input Hardware reset input that forces the device into the POR/BOR state; high-voltage tolerant with Schmitt trigger and weak pull-up.
14 SDO output SPI serial data output, connected to the host controller's SDI pin, used to read registers or monitor the command error bit.
15 VDD power_in Positive power supply input relative to VSS; specifications may not be met while VDD is below 2.7V, and a 0.1 µF bypass capacitor is recommended within 4 mm.
16 P2B passive Potentiometer 2 terminal B, the zero-scale connection; voltage must be between VSS and VDD.
17 P2W passive Potentiometer 2 wiper terminal; voltage must be between VSS and VDD.
18 P2A passive Potentiometer 2 terminal A, the full-scale connection (0x100 for 8-bit); voltage must be between VSS and VDD.
19 P3A passive Potentiometer 3 terminal A, the full-scale connection (0x100 for 8-bit); voltage must be between VSS and VDD.
20 P3W passive Potentiometer 3 wiper terminal; voltage must be between VSS and VDD.
21 EP passive Exposed thermal pad connected to the die substrate; tie to the same potential as VSS or leave unconnected, and it may serve as a heat sink.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-20-EP(4x4)
Category ADC/DAC/Data Conversion
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Nominal Resistance (-104 devices) RAB 80 100 120 kΩ -104 devices (±20%) 5
Supply Voltage VDD 2.7 5.5 V 4
Supply Voltage (serial interface only) VDD 1.8 2.7 V Serial Interface only 4
VDD start voltage to ensure wiper reset VBOR 1.65 V RAM retention voltage (VRAM) < VBOR 4
Delay after device exits Reset state TBORD 10 20 µs VDD > VBOR 4
Supply current, serial interface active IDD 450 µA VDD = 5.5V, CS = VIL, SCK @ 5 MHz, write all 0's to volatile Wiper 0 4
Supply current, serial interface inactive IDD 2.5 5 µA CS = VIH, VDD = 5.5V 4
Supply current, high-voltage active IDD 0.55 1 mA VDD = 5.5V, CS = VIHH, SCK @ 5 MHz, decrement volatile Wiper 0 4
Wiper resistance RW 75 160 Ω VDD = 5.5 V, IW = 2.0 mA, code = 00h 5
Wiper resistance RW 75 300 Ω VDD = 2.7 V, IW = 2.0 mA, code = 00h 5
Nominal resistance match (100k) /RABWC - RABMEAN//RABMEAN 0.2 1 % 100 k, MCP43X1 devices only 5
Resistance match RBW (100k) /RBWWC - RBWMEAN//RBWMEAN 0.25 1.25 % 100 k, Code = Full Scale 5
Nominal resistance tempco ΔRAB/ΔT 50 ppm/°C TA = -20°C to +70°C 5
Nominal resistance tempco ΔRAB/ΔT 100 ppm/°C TA = -40°C to +85°C 5
Nominal resistance tempco ΔRAB/ΔT 150 ppm/°C TA = -40°C to +125°C 5
Ratiometric tempco ΔVWB/ΔT 15 ppm/°C Code = Mid-scale (80h or 40h) 5
Resistor terminal input voltage range VA,VW,VB 0 5.5 V Vss to VDD; Note 5, Note 6 6
Maximum current through A, W or B IW 2.5 mA Worst case current through wiper at Full/Zero Scale 6
Leakage current into A, W or B IWL 100 nA MCP43X1 PxA = PxW = PxB = VSS 6
Full scale error (100k 8-bit) VWFSE -0.5 -0.1 LSb 100 k 8-bit, 3.0V ≤ VDD ≤ 5.5V 7
Zero scale error (100k 8-bit) VWZSE 0.1 0.5 LSb 100 k 8-bit, 3.0V ≤ VDD ≤ 5.5V 7
Potentiometer INL (8-bit) INL -1 0.5 1 LSb 8-bit 3.0V ≤ VDD ≤ 5.5V, MCP43X1 only (Note 2) 7
Potentiometer DNL (8-bit) DNL -0.5 0.25 0.5 LSb 8-bit 3.0V ≤ VDD ≤ 5.5V, MCP43X1 only (Note 2) 7
Bandwidth -3 dB (100k 8-bit) BW 100 kHz 100 k 8-bit, Code = 80h, load = 30 pF 7
Rheostat INL (100k 8-bit) R-INL -1 0.5 1 LSb 100 k 8-bit, 5.5V, IW = 45 µA 8
Rheostat INL (100k 8-bit) R-INL -1.5 0.25 1.5 LSb 100 k 8-bit, 3.0V, IW = 24 µA 8
Rheostat DNL (100k 8-bit) R-DNL -0.5 0.25 0.5 LSb 100 k 8-bit, 5.5V, IW = 45 µA 9
Capacitance (PA) CAW 75 pF f =1 MHz, Code = Full Scale 10
Capacitance (PW) CW 120 pF f =1 MHz, Code = Full Scale 10
Capacitance (PB) CBW 75 pF f =1 MHz, Code = Full Scale 10
Schmitt trigger high input threshold VIH 0.45 V 2.7V ≤ VDD ≤ 5.5V (min is 0.45 VDD) 10
Schmitt trigger high input threshold VIH 0.5 V 1.8V ≤ VDD ≤ 2.7V (min is 0.5 VDD) 10
Schmitt trigger low input threshold VIL 0.2 V max is 0.2VDD 10
High voltage input entry voltage VIHH 8.5 12.5 V Note 6 10
High voltage limit VMAX 12.5 V Pin can tolerate VMAX or less 10
Output low voltage (SDO) VOL 0 0.3 V IOL = 5 mA, VDD = 5.5V (max is 0.3VDD) 10
Output high voltage (SDO) VOH 0.7 V IOH = -2.5 mA, VDD = 5.5V (min is 0.7VDD) 10
Weak pull-up current IPU 1.75 mA Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VCS = 12.5V 11
Weak pull-up current CS pin IPU 170 µA CS pin, VDD = 5.5V, VCS = 3V 11
CS pull-up/pull-down resistance RCS 16 kΩ VDD = 5.5V, VCS = 3V 11
RESET pull-up resistance RRESET 16 kΩ VDD = 5.5V, VRESET = 0V 11
Input leakage current IIL -1 1 µA VIN = VDD (all pins) and VIN = VSS (all pins except RESET) 11
Pin capacitance CIN, COUT 10 pF fC = 20 MHz 11
Power supply sensitivity (8-bit) PSS 0.0015 0.0035 %/% VDD = 2.7V to 5.5V, VA = 2.7V, Code = 80h 11
RESET pulse width tRST 50 ns 12
RESET rising edge normal mode tRSTD 20 ns 12
SCK input frequency FSCK 10 MHz VDD = 2.7V to 5.5V 13
SCK input frequency FSCK 1 MHz VDD = 1.8V to 2.7V 13
SCK input high time TscH 45 ns VDD = 2.7V to 5.5V 13
SCK input low time TscL 45 ns VDD = 2.7V to 5.5V 13
SDO data output valid after SCK edge TscL2DOV 70 ns VDD = 2.7V to 5.5V 13
Voltage on VDD with respect to VSS VDD -0.6 7 V 3
Voltage on CS, SCK, SDI, SDI/SDO, RESET with respect to VSS -0.6 12.5 V 3
Maximum current into PxA, PxW, PxB pins -2.5 2.5 mA 3
Storage temperature -65 150 °C 3
Maximum junction temperature TJ 150 °C 3
Operating temperature range TA -40 125 °C 15
Thermal resistance, 20L-QFN θJA 43 °C/W 15

CAD (KiCad official)

  • Symbol: MCP4351-104E
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: mcp4351-104e-etched.step / mcp4351-104e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp4351-104e.step / mcp4351-104e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (88 pp, sha256 5666a7337dced900, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF