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MCP4251-503E
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Microchip Tech Digital Potentiometers, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MCP4251-503E
Microchip Tech · Digital Potentiometers · SOIC-14
MCP4251-503E from Microchip Tech, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | SPI chip select input; forcing CS to VIL enables serial commands and forcing it to VIHH enables high-voltage serial commands, and the pin is high-voltage tolerant with a Schmitt trigger input. |
| 2 | SCK | input | SPI serial clock input, high-voltage tolerant with a Schmitt trigger input. |
| 3 | SDI | input | SPI serial data input connected to the host controller SDO pin, high-voltage tolerant with a Schmitt trigger input. |
| 4 | VSS | power_in | Device ground reference; the positive supply VDD is specified relative to this pin. |
| 5 | P1B | passive | Potentiometer 1 terminal B, connected to the zero-scale wiper value (0x00); voltage on this terminal must be between VSS and VDD. |
| 6 | P1W | passive | Potentiometer 1 wiper terminal, which may carry positive or negative current; voltage on this terminal must be between VSS and VDD. |
| 7 | P1A | passive | Potentiometer 1 terminal A, connected to the full-scale wiper value; voltage on this terminal must be between VSS and VDD. |
| 8 | P0A | passive | Potentiometer 0 terminal A, connected to the full-scale wiper value; voltage on this terminal must be between VSS and VDD. |
| 9 | P0W | passive | Potentiometer 0 wiper terminal, which may carry positive or negative current; voltage on this terminal must be between VSS and VDD. |
| 10 | P0B | passive | Potentiometer 0 terminal B, connected to the zero-scale wiper value (0x00); voltage on this terminal must be between VSS and VDD. |
| 11 | NC | unconnected | No internal connection; should be connected to VDD or VSS to reduce possible noise coupling. |
| 12 | SHDN | input | Hardware shutdown input that forces the resistor network terminals into the hardware shutdown state; high-voltage tolerant with a Schmitt trigger input. |
| 13 | SDO | output | SPI serial data output connected to the host controller SDI pin, used to read device registers or monitor the command error bit; it is an open-drain output using the internal smart pull-up, so the output rate is limited by the pull-up unless an external pull-up is added. |
| 14 | VDD | power_in | Positive power supply input relative to VSS; electrical performance may not meet data sheet specifications while VDD is below 2.7V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-14 |
| Category | ADC/DAC/Data Conversion |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal resistance RAB (-503, 50 kΩ) | RAB | 40 | 50 | 60 | kΩ | ±20%; -503 devices (Note 1) | 5 |
| Supply voltage | VDD | 2.7 | 5.5 | V | 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices | 4 | |
| Supply voltage, serial interface only | VDD | 1.8 | 2.7 | V | Serial interface only | 4 | |
| High voltage on CS, SCK, SDI, SHDN | VHV | 12.5 | V | VDD ≥ 4.5V | 4 | ||
| VDD start voltage to ensure wiper reset | VBOR | 1.65 | V | RAM retention voltage (VRAM) < VBOR | 4 | ||
| Supply current, serial interface active | IDD | 450 | µA | Serial interface active, VDD = 5.5V, CS = VIL, SCK @ 5 MHz, write all 0's to volatile Wiper 0 (address 0h) | 4 | ||
| Supply current, serial interface inactive | IDD | 2.5 | 5 | µA | Serial interface inactive, CS = VIH, VDD = 5.5V | 4 | |
| Supply current, serial interface active, decrement | IDD | 0.55 | 1 | mA | Serial interface active, VDD = 5.5V, CS = VIHH, SCK @ 5 MHz, decrement volatile Wiper 0 (address 0h) | 4 | |
| Wiper resistance RW | RW | 75 | 160 | Ω | VDD = 5.5 V, IW = 2.0 mA, code = 00h | 5 | |
| Wiper resistance RW | RW | 75 | 300 | Ω | VDD = 2.7 V, IW = 2.0 mA, code = 00h | 5 | |
| Maximum current through A, W or B | IW | 2.5 | mA | Worst case current through wiper at full-scale or zero-scale (Note 6) | 5 | ||
| Full-scale error (MCP4XX1) | VWFSE | -0.8 | -0.1 | LSb | 8-bit code = 100h; 50 kΩ 8-bit 3.0V ≤ VDD ≤ 5.5V | 6 | |
| Zero-scale error (MCP4XX1) | VWZSE | 0.1 | 0.8 | LSb | 8-bit code = 00h; 50 kΩ 8-bit 3.0V ≤ VDD ≤ 5.5V | 6 | |
| Potentiometer integral non-linearity (MCP4XX1) | INL | -1 | 0.5 | 1 | LSb | 8-bit 3.0V ≤ VDD ≤ 5.5V; typ printed ±0.5 (Note 2) | 6 |
| Potentiometer differential non-linearity (MCP4XX1) | DNL | -0.5 | 0.25 | 0.5 | LSb | 8-bit 3.0V ≤ VDD ≤ 5.5V; typ printed ±0.25 (Note 2) | 6 |
| Rheostat integral non-linearity, 50 kΩ | R-INL | -1.5 | 0.5 | 1.5 | LSb | 50 kΩ 8-bit 5.5V, IW = 90 µA; typ printed ±0.5 | 7 |
| Rheostat integral non-linearity, 50 kΩ | R-INL | -2 | 1 | 2 | LSb | 3.0V, IW = 48 µA (Note 7) | 7 |
| Rheostat differential non-linearity, 50 kΩ | R-DNL | -0.5 | 0.25 | 0.5 | LSb | 50 kΩ 8-bit 5.5V, IW = 90 µA; typ printed ±0.25 | 8 |
| Schmitt trigger high input threshold | VIH | 0.45 | VDD | 2.7V ≤ VDD ≤ 5.5V | 9 | ||
| Schmitt trigger high input threshold | VIH | 0.5 | VDD | 1.8V ≤ VDD ≤ 2.7V | 9 | ||
| Schmitt trigger low input threshold | VIL | 0.2 | VDD | 9 | |||
| High voltage limit | VMAX | 12.5 | V | Pin can tolerate VMAX or less | 9 | ||
| Output low voltage (SDO) | VOL | 0.3 | VDD | VIOL = 5 mA, VDD = 5.5V | 9 | ||
| Output high voltage (SDO) | VOH | 0.7 | VDD | VIOH = -2.5 mA, VDD = 5.5V | 9 | ||
| Weak pull-up current | IPU | 1.75 | mA | Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VCS = 12.5V | 9 | ||
| Input leakage current | IIL | -1 | 1 | µA | VIN = VDD and VIN = VSS | 9 | |
| SCK input frequency | FSCK | 10 | MHz | VDD = 2.7V to 5.5V | 11 | ||
| SCK input frequency | FSCK | 1 | MHz | VDD = 1.8V to 2.7V | 11 | ||
| CS active (VIL or VIHH) to SCK↑ input | TcsA2scH | 60 | ns | 11 | |||
| SCK input high time | TscH | 45 | ns | VDD = 2.7V to 5.5V | 11 | ||
| SCK input low time | TscL | 45 | ns | VDD = 2.7V to 5.5V | 11 | ||
| Setup time of SDI input to SCK↑ edge | TDIV2scH | 10 | ns | 11 | |||
| Hold time of SDI input from SCK↑ edge | TscH2DIL | 20 | ns | 11 | |||
| CS inactive (VIH) to SDO output hi-impedance | TcsH2DOZ | 50 | ns | Note 1 | 11 | ||
| SDO data output valid after SCK↓ edge | TscL2DOV | 70 | ns | VDD = 2.7V to 5.5V | 11 | ||
| SDO data output valid after SCK↓ edge | TscL2DOV | 170 | ns | VDD = 1.8V to 2.7V | 11 | ||
| CS inactive (VIH) after SCK↑ edge | TscH2csI | 100 | ns | VDD = 2.7V to 5.5V | 11 | ||
| Hold time of CS inactive (VIH) to CS active (VIL or VIHH) | TcsA2csI | 50 | ns | 11 | |||
| Operating temperature range | TA | -40 | 125 | °C | Extended temperature range | 14 | |
| Storage temperature range | TA | -65 | 150 | °C | 14 | ||
| Voltage on VDD with respect to VSS | VDD | -0.6 | 7 | V | With respect to VSS | 3 | |
| Voltage on CS, SCK, SDI, SDI/SDO, SHDN with respect to VSS | VIN | -0.6 | 12.5 | V | With respect to VSS | 3 | |
| Voltage on all other pins (PxA, PxW, PxB, SDO) with respect to VSS | VIN | -0.3 | V | Maximum is VDD + 0.3 V | 3 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0, VI > VDD, VI > VPP on HV pins | 3 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VDD | 3 | |
| Maximum output current sunk by any output pin | 25 | mA | 3 | ||||
| Maximum output current sourced by any output pin | 25 | mA | 3 | ||||
| Maximum current out of VSS pin | 100 | mA | 3 | ||||
| Maximum current into VDD pin | 100 | mA | 3 | ||||
| Maximum current into PXA, PXW, PXB pins | -2.5 | 2.5 | mA | 3 | |||
| ESD protection, HBM | 4 | kV | HBM, on all pins (printed ≥ 4 kV) | 3 | |||
| Thermal resistance, 14L-SOIC, junction to ambient | θJA | 95.3 | °C/W | 14L-SOIC package | 14 | ||
| Nominal resistance tempco | ΔRAB/ΔT | 50 | ppm/°C | TA = -20°C to +70°C | 5 | ||
| Nominal resistance tempco | ΔRAB/ΔT | 100 | ppm/°C | TA = -40°C to +85°C | 5 | ||
| Nominal resistance tempco | ΔRAB/ΔT | 150 | ppm/°C | TA = -40°C to +125°C | 5 | ||
| Ratiometric tempco | ΔVWB/ΔT | 15 | ppm/°C | Code = Midscale (80h or 40h) | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | P = Plastic Dual In-line (PDIP) (300 mil), 8/14-lead SN = Plastic Small Outline (SOIC), (150 mil), 8-lead | 85 |
CAD (KiCad official)
- Symbol:
MCP4251-503E - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mcp4251-503e-etched.step/mcp4251-503e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4251-503e.step/mcp4251-503e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (88 pp, sha256
6c60b083b2ef0a92, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP4251-503E
**Microchip Tech** · Digital Potentiometers · SOIC-14
MCP4251-503E from Microchip Tech, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | SPI chip select input; forcing CS to VIL enables serial commands and forcing it to VIHH enables high-voltage serial commands, and the pin is high-voltage tolerant with a Schmitt trigger input. |
| 2 | SCK | input | SPI serial clock input, high-voltage tolerant with a Schmitt trigger input. |
| 3 | SDI | input | SPI serial data input connected to the host controller SDO pin, high-voltage tolerant with a Schmitt trigger input. |
| 4 | VSS | power_in | Device ground reference; the positive supply VDD is specified relative to this pin. |
| 5 | P1B | passive | Potentiometer 1 terminal B, connected to the zero-scale wiper value (0x00); voltage on this terminal must be between VSS and VDD. |
| 6 | P1W | passive | Potentiometer 1 wiper terminal, which may carry positive or negative current; voltage on this terminal must be between VSS and VDD. |
| 7 | P1A | passive | Potentiometer 1 terminal A, connected to the full-scale wiper value; voltage on this terminal must be between VSS and VDD. |
| 8 | P0A | passive | Potentiometer 0 terminal A, connected to the full-scale wiper value; voltage on this terminal must be between VSS and VDD. |
| 9 | P0W | passive | Potentiometer 0 wiper terminal, which may carry positive or negative current; voltage on this terminal must be between VSS and VDD. |
| 10 | P0B | passive | Potentiometer 0 terminal B, connected to the zero-scale wiper value (0x00); voltage on this terminal must be between VSS and VDD. |
| 11 | NC | unconnected | No internal connection; should be connected to VDD or VSS to reduce possible noise coupling. |
| 12 | SHDN | input | Hardware shutdown input that forces the resistor network terminals into the hardware shutdown state; high-voltage tolerant with a Schmitt trigger input. |
| 13 | SDO | output | SPI serial data output connected to the host controller SDI pin, used to read device registers or monitor the command error bit; it is an open-drain output using the internal smart pull-up, so the output rate is limited by the pull-up unless an external pull-up is added. |
| 14 | VDD | power_in | Positive power supply input relative to VSS; electrical performance may not meet data sheet specifications while VDD is below 2.7V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-14 |
| Category | ADC/DAC/Data Conversion |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal resistance RAB (-503, 50 kΩ) | RAB | 40 | 50 | 60 | kΩ | ±20%; -503 devices (Note 1) | 5 |
| Supply voltage | VDD | 2.7 | | 5.5 | V | 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices | 4 |
| Supply voltage, serial interface only | VDD | 1.8 | | 2.7 | V | Serial interface only | 4 |
| High voltage on CS, SCK, SDI, SHDN | VHV | | | 12.5 | V | VDD ≥ 4.5V | 4 |
| VDD start voltage to ensure wiper reset | VBOR | | | 1.65 | V | RAM retention voltage (VRAM) < VBOR | 4 |
| Supply current, serial interface active | IDD | | | 450 | µA | Serial interface active, VDD = 5.5V, CS = VIL, SCK @ 5 MHz, write all 0's to volatile Wiper 0 (address 0h) | 4 |
| Supply current, serial interface inactive | IDD | | 2.5 | 5 | µA | Serial interface inactive, CS = VIH, VDD = 5.5V | 4 |
| Supply current, serial interface active, decrement | IDD | | 0.55 | 1 | mA | Serial interface active, VDD = 5.5V, CS = VIHH, SCK @ 5 MHz, decrement volatile Wiper 0 (address 0h) | 4 |
| Wiper resistance RW | RW | | 75 | 160 | Ω | VDD = 5.5 V, IW = 2.0 mA, code = 00h | 5 |
| Wiper resistance RW | RW | | 75 | 300 | Ω | VDD = 2.7 V, IW = 2.0 mA, code = 00h | 5 |
| Maximum current through A, W or B | IW | | | 2.5 | mA | Worst case current through wiper at full-scale or zero-scale (Note 6) | 5 |
| Full-scale error (MCP4XX1) | VWFSE | -0.8 | -0.1 | | LSb | 8-bit code = 100h; 50 kΩ 8-bit 3.0V ≤ VDD ≤ 5.5V | 6 |
| Zero-scale error (MCP4XX1) | VWZSE | | 0.1 | 0.8 | LSb | 8-bit code = 00h; 50 kΩ 8-bit 3.0V ≤ VDD ≤ 5.5V | 6 |
| Potentiometer integral non-linearity (MCP4XX1) | INL | -1 | 0.5 | 1 | LSb | 8-bit 3.0V ≤ VDD ≤ 5.5V; typ printed ±0.5 (Note 2) | 6 |
| Potentiometer differential non-linearity (MCP4XX1) | DNL | -0.5 | 0.25 | 0.5 | LSb | 8-bit 3.0V ≤ VDD ≤ 5.5V; typ printed ±0.25 (Note 2) | 6 |
| Rheostat integral non-linearity, 50 kΩ | R-INL | -1.5 | 0.5 | 1.5 | LSb | 50 kΩ 8-bit 5.5V, IW = 90 µA; typ printed ±0.5 | 7 |
| Rheostat integral non-linearity, 50 kΩ | R-INL | -2 | 1 | 2 | LSb | 3.0V, IW = 48 µA (Note 7) | 7 |
| Rheostat differential non-linearity, 50 kΩ | R-DNL | -0.5 | 0.25 | 0.5 | LSb | 50 kΩ 8-bit 5.5V, IW = 90 µA; typ printed ±0.25 | 8 |
| Schmitt trigger high input threshold | VIH | 0.45 | | | VDD | 2.7V ≤ VDD ≤ 5.5V | 9 |
| Schmitt trigger high input threshold | VIH | 0.5 | | | VDD | 1.8V ≤ VDD ≤ 2.7V | 9 |
| Schmitt trigger low input threshold | VIL | | | 0.2 | VDD | | 9 |
| High voltage limit | VMAX | | | 12.5 | V | Pin can tolerate VMAX or less | 9 |
| Output low voltage (SDO) | VOL | | | 0.3 | VDD | VIOL = 5 mA, VDD = 5.5V | 9 |
| Output high voltage (SDO) | VOH | 0.7 | | | VDD | VIOH = -2.5 mA, VDD = 5.5V | 9 |
| Weak pull-up current | IPU | | | 1.75 | mA | Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VCS = 12.5V | 9 |
| Input leakage current | IIL | -1 | | 1 | µA | VIN = VDD and VIN = VSS | 9 |
| SCK input frequency | FSCK | | | 10 | MHz | VDD = 2.7V to 5.5V | 11 |
| SCK input frequency | FSCK | | | 1 | MHz | VDD = 1.8V to 2.7V | 11 |
| CS active (VIL or VIHH) to SCK↑ input | TcsA2scH | 60 | | | ns | | 11 |
| SCK input high time | TscH | 45 | | | ns | VDD = 2.7V to 5.5V | 11 |
| SCK input low time | TscL | 45 | | | ns | VDD = 2.7V to 5.5V | 11 |
| Setup time of SDI input to SCK↑ edge | TDIV2scH | 10 | | | ns | | 11 |
| Hold time of SDI input from SCK↑ edge | TscH2DIL | 20 | | | ns | | 11 |
| CS inactive (VIH) to SDO output hi-impedance | TcsH2DOZ | | | 50 | ns | Note 1 | 11 |
| SDO data output valid after SCK↓ edge | TscL2DOV | | | 70 | ns | VDD = 2.7V to 5.5V | 11 |
| SDO data output valid after SCK↓ edge | TscL2DOV | | | 170 | ns | VDD = 1.8V to 2.7V | 11 |
| CS inactive (VIH) after SCK↑ edge | TscH2csI | 100 | | | ns | VDD = 2.7V to 5.5V | 11 |
| Hold time of CS inactive (VIH) to CS active (VIL or VIHH) | TcsA2csI | 50 | | | ns | | 11 |
| Operating temperature range | TA | -40 | | 125 | °C | Extended temperature range | 14 |
| Storage temperature range | TA | -65 | | 150 | °C | | 14 |
| Voltage on VDD with respect to VSS | VDD | -0.6 | | 7 | V | With respect to VSS | 3 |
| Voltage on CS, SCK, SDI, SDI/SDO, SHDN with respect to VSS | VIN | -0.6 | | 12.5 | V | With respect to VSS | 3 |
| Voltage on all other pins (PxA, PxW, PxB, SDO) with respect to VSS | VIN | -0.3 | | | V | Maximum is VDD + 0.3 V | 3 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < 0, VI > VDD, VI > VPP on HV pins | 3 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < 0 or VO > VDD | 3 |
| Maximum output current sunk by any output pin | | | | 25 | mA | | 3 |
| Maximum output current sourced by any output pin | | | | 25 | mA | | 3 |
| Maximum current out of VSS pin | | | | 100 | mA | | 3 |
| Maximum current into VDD pin | | | | 100 | mA | | 3 |
| Maximum current into PXA, PXW, PXB pins | | -2.5 | | 2.5 | mA | | 3 |
| ESD protection, HBM | | 4 | | | kV | HBM, on all pins (printed ≥ 4 kV) | 3 |
| Thermal resistance, 14L-SOIC, junction to ambient | θJA | | 95.3 | | °C/W | 14L-SOIC package | 14 |
| Nominal resistance tempco | ΔRAB/ΔT | | 50 | | ppm/°C | TA = -20°C to +70°C | 5 |
| Nominal resistance tempco | ΔRAB/ΔT | | 100 | | ppm/°C | TA = -40°C to +85°C | 5 |
| Nominal resistance tempco | ΔRAB/ΔT | | 150 | | ppm/°C | TA = -40°C to +125°C | 5 |
| Ratiometric tempco | ΔVWB/ΔT | | 15 | | ppm/°C | Code = Midscale (80h or 40h) | 5 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | P = Plastic Dual In-line (PDIP) (300 mil), 8/14-lead SN = Plastic Small Outline (SOIC), (150 mil), 8-lead | 85 |
## CAD (KiCad official)
- Symbol: `MCP4251-503E`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `mcp4251-503e-etched.step` / `mcp4251-503e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp4251-503e.step` / `mcp4251-503e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/mcp4251-503e-datasheet.pdf) (88 pp, sha256 `6c60b083b2ef0a92`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp4251-503e-datasheet.pdf)