component
MCP4232-502E
Public Made by Adomby adom
Microchip Tech Digital Potentiometers, MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MCP4232-502E
Microchip Tech · Digital Potentiometers · MSOP-10
MCP4232-502E from Microchip Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Forcing CS to VIL enables the serial commands, and forcing it to VIHH enables the high-voltage serial commands. |
| 2 | SCK | input | SPI clock input, high-voltage tolerant with Schmitt trigger input and internal weak pull-up. |
| 3 | SDI | input | SPI serial data input, connected to the host controller SDO pin, high-voltage tolerant with Schmitt trigger input. |
| 4 | VSS | power_in | Device ground reference; all terminal voltages must be between VSS and VDD. |
| 5 | P1B | passive | Potentiometer 1 terminal B, with no polarity relative to terminals W or A, voltage must be between VSS and VDD. |
| 6 | P1W | passive | Potentiometer 1 wiper terminal, which can support both positive and negative current, voltage must be between VSS and VDD. |
| 7 | P0W | passive | Potentiometer 0 wiper terminal, which can support both positive and negative current, voltage must be between VSS and VDD. |
| 8 | P0B | passive | Potentiometer 0 terminal B, with no polarity relative to terminals W or A, voltage must be between VSS and VDD. |
| 9 | SDO | output | SPI serial data output connected to the host controller SDI pin, an open drain output using the internal smart pull-up. |
| 10 | VDD | power_in | Positive power supply input relative to VSS; electrical performance may not meet specifications while VDD is below 2.7V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | MSOP-10 |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal resistance RAB | RAB | 4 | 5 | 6 | kΩ | -502 devices (Note 1) | 5 |
| RAB resistance tolerance | -20 | 20 | % | (± 20%) | 5 | ||
| Supply voltage | VDD | 2.7 | 5.5 | V | 4 | ||
| Supply voltage serial interface only | VDD | 1.8 | 2.7 | V | Serial Interface only. | 4 | |
| VDD start voltage to ensure wiper reset | VBOR | 1.65 | V | RAM retention voltage (VRAM) < VBOR | 4 | ||
| Delay after device exits reset state | TBORD | 10 | 20 | µs | (VDD > VBOR) | 4 | |
| CS, SCK, SDI, SDO, SHDN high voltage range | VHV | 12.5 | V | VDD ≥ 4.5V | 4 | ||
| Supply current serial interface active | IDD | 450 | µA | Serial Interface Active, VDD = 5.5V, CS = VIL, SCK @ 5 MHz, write all 0’s to volatile Wiper 0 (address 0h) | 4 | ||
| Supply current serial interface inactive | IDD | 2.5 | 5 | µA | Serial Interface Inactive, CS = VIH, VDD = 5.5V | 4 | |
| Supply current serial interface active CS = VIHH | IDD | 0.55 | 1 | mA | Serial Interface Active, VDD = 5.5V, CS = VIHH, SCK @ 5 MHz, decrement volatile Wiper 0 (address 0h) | 4 | |
| Wiper resistance | RW | 75 | 160 | Ω | VDD = 5.5 V, IW = 2.0 mA, code = 00h | 5 | |
| Wiper resistance | RW | 75 | 300 | Ω | VDD = 2.7 V, IW = 2.0 mA, code = 00h | 5 | |
| Resistance match RBW | /RBW0 - RBW1/ / RBW | 0.25 | 1.5 | % | MCP42X2 devices only, Code = Full-Scale | 5 | |
| Maximum current through A, W or B | IW | 2.5 | mA | Worst case current through wiper when wiper is either Full-Scale or Zero Scale. | 5 | ||
| Rheostat integral non-linearity 5 kΩ 7-bit | R-INL | -1.125 | 0.5 | 1.125 | LSb | 7-bit 5.5V, IW = 900 µA | 7 |
| Rheostat integral non-linearity 5 kΩ 7-bit | R-INL | -6 | 4.5 | 6 | LSb | 7-bit 3.0V, IW = 480 µA (Note 7) | 7 |
| Rheostat differential non-linearity 5 kΩ 7-bit | R-DNL | -0.375 | 0.25 | 0.375 | LSb | 7-bit 5.5V, IW = 900 µA | 8 |
| Rheostat differential non-linearity 5 kΩ 7-bit | R-DNL | -0.75 | 0.5 | 0.75 | LSb | 7-bit 3.0V (Note 7) | 8 |
| Weak pull-up current | IPU | 1.75 | mA | Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VCS = 12.5V | 9 | ||
| Input leakage current | IIL | -1 | 1 | µA | VIN = VDD and VIN = VSS | 9 | |
| Power supply sensitivity 7-bit | PSS | 0.0015 | 0.0035 | %/% | 7-bit VDD = 2.7V to 5.5V, VA = 2.7V, Code = 40h | 10 | |
| Bandwidth -3 dB 5 kΩ 7-bit | BW | 2 | MHz | 7-bit Code = 40h, load = 30 pF | 6 | ||
| Voltage on VDD with respect to VSS | VDD | -0.6 | 7 | V | 3 | ||
| Voltage on CS, SCK, SDI, SDI/SDO and SHDN with respect to VSS | -0.6 | 12.5 | V | 3 | |||
| Voltage on all other pins with respect to VSS | -0.3 | V | PxA, PxW, PxB and SDO; upper limit is VDD + 0.3V | 3 | |||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0, VI > VDD, VI > VPP ON HV pins | 3 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VDD | 3 | |
| Maximum output current sunk by any output pin | 25 | mA | 3 | ||||
| Maximum output current sourced by any output pin | 25 | mA | 3 | ||||
| Maximum current out of VSS pin | 100 | mA | 3 | ||||
| Maximum current into VDD pin | 100 | mA | 3 | ||||
| Maximum current into PXA, PXW and PXB pins | -2.5 | 2.5 | mA | 3 | |||
| Storage temperature | TSTG | -65 | 150 | °C | 3 | ||
| Ambient temperature with power applied | TA | -40 | 125 | °C | 3 | ||
| Soldering temperature of leads | 300 | °C | 10 seconds | 3 | |||
| Maximum junction temperature | TJ | 150 | °C | 3 | |||
| ESD protection HBM | 4 | kV | HBM | 3 | |||
| ESD protection MM | 300 | V | MM | 3 | |||
| Operating temperature range | TA | -40 | 125 | °C | 14 | ||
| Thermal resistance 10L-MSOP | θJA | 211 | °C/W | 14 | |||
| Nominal resistance tempco | ΔRAB/ΔT | 50 | ppm/°C | TA = -20°C to +70°C | 5 | ||
| Nominal resistance tempco | ΔRAB/ΔT | 100 | ppm/°C | TA = -40°C to +85°C | 5 | ||
| Nominal resistance tempco | ΔRAB/ΔT | 150 | ppm/°C | TA = -40°C to +125°C | 5 | ||
| Ratiometric tempco | ΔVWB/ΔT | 15 | ppm/°C | Code = Midscale (80h or 40h) | 5 | ||
| Leakage current into A, W or B | IWL | 100 | nA | MCP4XX2 PxB = PxW = VSS | 5 | ||
| CS pull-up/pull-down resistance | RCS | 16 | kΩ | VDD = 5.5V, VCS = 3V | 9 | ||
| CS pin pull-up/pull-down current | 170 | µA | CS pin, VDD = 5.5V, VCS = 3V | 9 | |||
| Pin capacitance | CIN, COUT | 10 | pF | fC = 20 MHz | 9 | ||
| Capacitance (PA) | CAW | 75 | pF | f = 1 MHz, Code = Full-Scale | 8 | ||
| Capacitance (PW) | CW | 120 | pF | f = 1 MHz, Code = Full-Scale | 8 | ||
| Capacitance (PB) | CBW | 75 | pF | f = 1 MHz, Code = Full-Scale | 8 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | P = Plastic Dual In-line (PDIP) (300 mil), 8/14-lead SN = Plastic Small Outline (SOIC), (150 mil), 8-lead | 85 |
CAD (KiCad official)
- Symbol:
MCP4232-502E - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
mcp4232-502e-etched.step/mcp4232-502e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4232-502e.step/mcp4232-502e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (88 pp, sha256
6c60b083b2ef0a92, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP4232-502E
**Microchip Tech** · Digital Potentiometers · MSOP-10
MCP4232-502E from Microchip Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Forcing CS to VIL enables the serial commands, and forcing it to VIHH enables the high-voltage serial commands. |
| 2 | SCK | input | SPI clock input, high-voltage tolerant with Schmitt trigger input and internal weak pull-up. |
| 3 | SDI | input | SPI serial data input, connected to the host controller SDO pin, high-voltage tolerant with Schmitt trigger input. |
| 4 | VSS | power_in | Device ground reference; all terminal voltages must be between VSS and VDD. |
| 5 | P1B | passive | Potentiometer 1 terminal B, with no polarity relative to terminals W or A, voltage must be between VSS and VDD. |
| 6 | P1W | passive | Potentiometer 1 wiper terminal, which can support both positive and negative current, voltage must be between VSS and VDD. |
| 7 | P0W | passive | Potentiometer 0 wiper terminal, which can support both positive and negative current, voltage must be between VSS and VDD. |
| 8 | P0B | passive | Potentiometer 0 terminal B, with no polarity relative to terminals W or A, voltage must be between VSS and VDD. |
| 9 | SDO | output | SPI serial data output connected to the host controller SDI pin, an open drain output using the internal smart pull-up. |
| 10 | VDD | power_in | Positive power supply input relative to VSS; electrical performance may not meet specifications while VDD is below 2.7V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | MSOP-10 |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal resistance RAB | RAB | 4 | 5 | 6 | kΩ | -502 devices (Note 1) | 5 |
| RAB resistance tolerance | | -20 | | 20 | % | (± 20%) | 5 |
| Supply voltage | VDD | 2.7 | | 5.5 | V | | 4 |
| Supply voltage serial interface only | VDD | 1.8 | | 2.7 | V | Serial Interface only. | 4 |
| VDD start voltage to ensure wiper reset | VBOR | | | 1.65 | V | RAM retention voltage (VRAM) < VBOR | 4 |
| Delay after device exits reset state | TBORD | | 10 | 20 | µs | (VDD > VBOR) | 4 |
| CS, SCK, SDI, SDO, SHDN high voltage range | VHV | | | 12.5 | V | VDD ≥ 4.5V | 4 |
| Supply current serial interface active | IDD | | | 450 | µA | Serial Interface Active, VDD = 5.5V, CS = VIL, SCK @ 5 MHz, write all 0’s to volatile Wiper 0 (address 0h) | 4 |
| Supply current serial interface inactive | IDD | | 2.5 | 5 | µA | Serial Interface Inactive, CS = VIH, VDD = 5.5V | 4 |
| Supply current serial interface active CS = VIHH | IDD | | 0.55 | 1 | mA | Serial Interface Active, VDD = 5.5V, CS = VIHH, SCK @ 5 MHz, decrement volatile Wiper 0 (address 0h) | 4 |
| Wiper resistance | RW | | 75 | 160 | Ω | VDD = 5.5 V, IW = 2.0 mA, code = 00h | 5 |
| Wiper resistance | RW | | 75 | 300 | Ω | VDD = 2.7 V, IW = 2.0 mA, code = 00h | 5 |
| Resistance match RBW | /RBW0 - RBW1/ / RBW | | 0.25 | 1.5 | % | MCP42X2 devices only, Code = Full-Scale | 5 |
| Maximum current through A, W or B | IW | | | 2.5 | mA | Worst case current through wiper when wiper is either Full-Scale or Zero Scale. | 5 |
| Rheostat integral non-linearity 5 kΩ 7-bit | R-INL | -1.125 | 0.5 | 1.125 | LSb | 7-bit 5.5V, IW = 900 µA | 7 |
| Rheostat integral non-linearity 5 kΩ 7-bit | R-INL | -6 | 4.5 | 6 | LSb | 7-bit 3.0V, IW = 480 µA (Note 7) | 7 |
| Rheostat differential non-linearity 5 kΩ 7-bit | R-DNL | -0.375 | 0.25 | 0.375 | LSb | 7-bit 5.5V, IW = 900 µA | 8 |
| Rheostat differential non-linearity 5 kΩ 7-bit | R-DNL | -0.75 | 0.5 | 0.75 | LSb | 7-bit 3.0V (Note 7) | 8 |
| Weak pull-up current | IPU | | | 1.75 | mA | Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VCS = 12.5V | 9 |
| Input leakage current | IIL | -1 | | 1 | µA | VIN = VDD and VIN = VSS | 9 |
| Power supply sensitivity 7-bit | PSS | | 0.0015 | 0.0035 | %/% | 7-bit VDD = 2.7V to 5.5V, VA = 2.7V, Code = 40h | 10 |
| Bandwidth -3 dB 5 kΩ 7-bit | BW | | 2 | | MHz | 7-bit Code = 40h, load = 30 pF | 6 |
| Voltage on VDD with respect to VSS | VDD | -0.6 | | 7 | V | | 3 |
| Voltage on CS, SCK, SDI, SDI/SDO and SHDN with respect to VSS | | -0.6 | | 12.5 | V | | 3 |
| Voltage on all other pins with respect to VSS | | -0.3 | | | V | PxA, PxW, PxB and SDO; upper limit is VDD + 0.3V | 3 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < 0, VI > VDD, VI > VPP ON HV pins | 3 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < 0 or VO > VDD | 3 |
| Maximum output current sunk by any output pin | | | | 25 | mA | | 3 |
| Maximum output current sourced by any output pin | | | | 25 | mA | | 3 |
| Maximum current out of VSS pin | | | | 100 | mA | | 3 |
| Maximum current into VDD pin | | | | 100 | mA | | 3 |
| Maximum current into PXA, PXW and PXB pins | | -2.5 | | 2.5 | mA | | 3 |
| Storage temperature | TSTG | -65 | | 150 | °C | | 3 |
| Ambient temperature with power applied | TA | -40 | | 125 | °C | | 3 |
| Soldering temperature of leads | | | | 300 | °C | 10 seconds | 3 |
| Maximum junction temperature | TJ | | | 150 | °C | | 3 |
| ESD protection HBM | | 4 | | | kV | HBM | 3 |
| ESD protection MM | | 300 | | | V | MM | 3 |
| Operating temperature range | TA | -40 | | 125 | °C | | 14 |
| Thermal resistance 10L-MSOP | θJA | | 211 | | °C/W | | 14 |
| Nominal resistance tempco | ΔRAB/ΔT | | 50 | | ppm/°C | TA = -20°C to +70°C | 5 |
| Nominal resistance tempco | ΔRAB/ΔT | | 100 | | ppm/°C | TA = -40°C to +85°C | 5 |
| Nominal resistance tempco | ΔRAB/ΔT | | 150 | | ppm/°C | TA = -40°C to +125°C | 5 |
| Ratiometric tempco | ΔVWB/ΔT | | 15 | | ppm/°C | Code = Midscale (80h or 40h) | 5 |
| Leakage current into A, W or B | IWL | | 100 | | nA | MCP4XX2 PxB = PxW = VSS | 5 |
| CS pull-up/pull-down resistance | RCS | | 16 | | kΩ | VDD = 5.5V, VCS = 3V | 9 |
| CS pin pull-up/pull-down current | | | 170 | | µA | CS pin, VDD = 5.5V, VCS = 3V | 9 |
| Pin capacitance | CIN, COUT | | 10 | | pF | fC = 20 MHz | 9 |
| Capacitance (PA) | CAW | | 75 | | pF | f = 1 MHz, Code = Full-Scale | 8 |
| Capacitance (PW) | CW | | 120 | | pF | f = 1 MHz, Code = Full-Scale | 8 |
| Capacitance (PB) | CBW | | 75 | | pF | f = 1 MHz, Code = Full-Scale | 8 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | P = Plastic Dual In-line (PDIP) (300 mil), 8/14-lead SN = Plastic Small Outline (SOIC), (150 mil), 8-lead | 85 |
## CAD (KiCad official)
- Symbol: `MCP4232-502E`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files: `mcp4232-502e-etched.step` / `mcp4232-502e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp4232-502e.step` / `mcp4232-502e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/mcp4232-502e-datasheet.pdf) (88 pp, sha256 `6c60b083b2ef0a92`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp4232-502e-datasheet.pdf)