# MCP42100T-I

**Microchip Tech** · Digital Potentiometers · SOIC-14

MCP42100T-I from Microchip Tech, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | SPI chip select; it executes a new command after the command has been loaded into the shift register, and it has a Schmitt Trigger input. |
| 2 | SCK | input | SPI serial clock; data is clocked into SI on the rising edge and out of SO on the falling edge, the pin is gated to CS, and it has a Schmitt Trigger input. |
| 3 | SI | input | SPI serial data input for the command and data bytes, gated to CS, with a Schmitt Trigger input. |
| 4 | VSS | power_in | Ground reference pin for the device. |
| 5 | PB1 | passive | Terminal B connection for potentiometer 1 (dual MCP42XXX only). |
| 6 | PW1 | passive | Wiper connection for potentiometer 1 (dual MCP42XXX only). |
| 7 | PA1 | passive | Terminal A connection for potentiometer 1 (dual MCP42XXX only). |
| 8 | PA0 | passive | Terminal A connection for potentiometer 0. |
| 9 | PW0 | passive | Wiper connection for potentiometer 0. |
| 10 | PB0 | passive | Terminal B connection for potentiometer 0. |
| 11 | RS | input | Hardware reset that sets all potentiometers to mid-scale (Code 80h) when held low for at least 150 ns; it should not be toggled low while CS is low, it has an active pull-up, and it must not be left floating. |
| 12 | SHDN | input | Hardware shutdown input; pulling it low opens the A terminal and connects B and W for all potentiometers, it should not be toggled low while CS is low, it has a Schmitt Trigger input, and it must not be left floating. |
| 13 | SO | output | Serial data output for daisy-chaining devices; it is a push-pull output that clocks data out on the falling edge of SCK and drives logic low when CS is high. |
| 14 | VDD | power_in | Positive supply pin; the device operates from a single 2.7 V to 5.5 V supply. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-14 |
| Category | ADC/DAC/Data Conversion |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal Resistance | R | 70 | 100 | 130 | kΩ | TA = +25°C (Note 1) | 4 |
| Wiper Resistance | RW |  | 125 | 175 | Ω | VDD = 5.5V, IW = 1 mA, code 00h | 4 |
| Wiper Resistance | RW |  | 175 | 250 | Ω | VDD = 2.7V, IW = 1 mA, code 00h | 4 |
| Wiper Current | IW | -1 |  | 1 | mA |  | 4 |
| Resolution | N | 8 |  |  | Bits |  | 4 |
| Monotonicity | N | 8 |  |  | Bits |  | 4 |
| Differential Non-Linearity | DNL | -1 |  | 1 | LSB | Note 3 | 4 |
| Integral Non-Linearity | INL | -1 |  | 1 | LSB | Note 3 | 4 |
| Rheostat Differential Non-Linearity | R-DNL | -1 |  | 1 | LSB | Note 2 | 4 |
| Rheostat Integral Non-Linearity | R-INL | -1 |  | 1 | LSB | Note 2 | 4 |
| Full-Scale Error | VWFSE | -1 | -0.25 | 0 | LSB | Code FFh, VDD = 5V, see Figure 2-25 | 4 |
| Full-Scale Error | VWFSE | -1 | -0.35 | 0 | LSB | Code FFh, VDD = 3V, see Figure 2-25 | 4 |
| Zero-Scale Error | VWZSE | 0 | 0.25 | 1 | LSB | Code 00h, VDD = 5V, see Figure 2-25 | 4 |
| Zero-Scale Error | VWZSE | 0 | 0.35 | 1 | LSB | Code 00h, VDD = 3V, see Figure 2-25 | 4 |
| Voltage Range | VA,B,W | 0 |  |  | V | Note 4 | 4 |
| Low-Level Output Voltage | VOL |  |  | 0.4 | V | IOL = 2.1 mA, VDD = 5V | 4 |
| Input Leakage Current | ILI | -1 |  | 1 | µA | CS = VDD, VIN = VSS or VDD, includes VA SHDN=0 | 4 |
| Operating Voltage Range | VDD | 2.7 |  | 5.5 | V |  | 4 |
| Supply Current, Active | IDDA |  | 340 | 500 | µA | VDD = 5.5V, CS = VSS, fSCK = 10 MHz, SO = Open, Code FFh (Note 6) | 4 |
| Supply Current, Static | IDDS |  | 0.01 | 1 | µA | CS, SHDN, RS = VDD = 5.5V, SO = Open (Note 6) | 4 |
| Power Supply Sensitivity | PSS |  | 0.0015 | 0.0035 | %/% | VDD = 4.5V - 5.5V, VA = 4.5V, Code 80h | 4 |
| Clock Frequency | FCLK |  |  | 10 | MHz | VDD = 5V (Note 1) | 5 |
| Clock High Time | tHI | 40 |  |  | ns |  | 5 |
| Clock Low Time | tLO | 40 |  |  | ns |  | 5 |
| CS Fall to First Rising CLK Edge | tCSSR | 40 |  |  | ns |  | 5 |
| Data Input Setup Time | tSU | 40 |  |  | ns |  | 5 |
| Data Input Hold Time | tHD | 10 |  |  | ns |  | 5 |
| SCK Fall to SO Valid Propagation Delay | tDO |  | 80 |  | ns | CL = 30 pF (Note 2) | 5 |
| SCK Rise to CS Rise Hold Time | tCHS | 30 |  |  | ns |  | 5 |
| SCK Rise to CS Fall Delay | tCS0 | 10 |  |  | ns |  | 5 |
| CS Rise to CLK Rise Hold | tCS1 | 100 |  |  | ns |  | 5 |
| CS High Time | tCSH | 40 |  |  | ns |  | 5 |
| Reset Pulse Width | tRS | 150 |  |  | ns | Note 2 | 5 |
| RS Rising to CS Falling Delay Time | tRSCS | 150 |  |  | ns | Note 2 | 5 |
| CS rising to RS or SHDN falling delay time | tSE | 40 |  |  | ns | Note 3 | 5 |
| CS low time | tCSL | 100 |  |  | ns | Note 3 | 5 |
| Shutdown Pulse Width | tSH | 150 |  |  | ns | Note 3 | 5 |
| All inputs and outputs w.r.t. VSS |  | -0.6 |  |  | V | Upper limit printed as VDD + 1.0V | 5 |
| Storage temperature |  | -60 |  | 150 | °C |  | 5 |
| Ambient temp. with power applied |  | -60 |  | 125 | °C |  | 5 |
| ESD protection on all pins |  | 2 |  |  | kV |  | 5 |
| Operating temperature range (industrial) | TA | -40 |  | 85 | °C | Electrical characteristics header, VDD = +2.7V to 5.5V | 4 |
| Rheostat Tempco | ∆RAB/∆T |  | 800 |  | ppm/°C |  | 4 |
| Voltage Divider Tempco | ∆VW/∆T |  | 1 |  | ppm/°C | Code 80h | 4 |
| Bandwidth -3dB | BW |  | 145 |  | MHz | VB = 0V, Measured at Code 80h, Output Load = 30 PF | 4 |
| Settling Time | tS |  | 18 |  | µS | VA = VDD,VB = 0V, ±1% Error Band, Transition from Code 00h to Code 80h, Output Load = 30 pF | 4 |
| Resistor Noise Voltage | eNWB |  | 29 |  | nV/√Hz | VA = Open, Code 80h, f =1 kHz | 4 |
| Crosstalk | CT |  | -95 |  | dB | VA = VDD, VB = 0V (Note 5) | 4 |
| Capacitance (CA or CB) | CA or CB |  | 11 |  | pF | f =1 MHz, Code = 80h, see Figure 2-30 | 4 |
| Capacitance | CW |  | 5.6 |  | pF | f =1 MHz, Code = 80h, see Figure 2-30 | 4 |
| Pin Capacitance (All inputs/outputs) | CIN, COUT |  | 10 |  | pF | VDD = 5.0V, TA = +25°C, fc = 1 MHz | 4 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | 8-Lead Plastic Small Outline (SN), Narrow, 150 mil (SOIC) Foot Angle φ 048048 | 25 |

## CAD (KiCad official)

- Symbol: `MCP42100T-I`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `mcp42100t-i-etched.step` / `mcp42100t-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp42100t-i.step` / `mcp42100t-i.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/mcp42100t-i-datasheet.pdf) (32 pp, sha256 `6bee8156c8b9f1f6`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mcp42100t-i-datasheet.pdf)