# MCP41HV51-104E

**Microchip Tech** · Digital Potentiometers · TSSOP-14

MCP41HV51-104E from Microchip Tech, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VL | power_in | Positive digital power supply input referenced to DGND, operating from 1.8V to 5.5V, with a decoupling capacitor to DGND recommended and performance outside specification below VL 2.7V (Vmin). |
| 2 | SCK | input | SPI serial clock input with Schmitt trigger, input-only because the device is an SPI slave. |
| 3 | CS | input | Serial interface chip select input with Schmitt trigger, where forcing CS to VIL enables serial commands. |
| 4 | SDI | input | SPI serial data input with Schmitt trigger, connected to the host controller SDO pin. |
| 5 | SDO | output | SPI serial data output used to read the Wiper and TCON registers or monitor the command error bit, connected to the host controller SDI pin. |
| 6 | WLAT | input | Wiper latch enable input with Schmitt trigger, where 0 transfers the received SPIBUF value to the wiper register and 1 holds the received data in SPIBUF. |
| 7 | SHDN | input | Shutdown input with Schmitt trigger that forces the resistor network terminals into the hardware shutdown state. |
| 8 | DGND | power_in | Digital ground reference for the device, to which VL is referenced. |
| 9 | NC | unconnected | Pin not internally connected to the die; to reduce noise coupling, connect to either DGND or VL. |
| 10 | V- | power_in | Analog negative supply voltage that must not have a higher potential than the DGND pin. |
| 11 | P0B | bidirectional | Potentiometer 0 Terminal B, the fixed connection to the zero-scale wiper value (0x00), which can carry positive or negative current with voltage between V+ and V-. |
| 12 | P0W | bidirectional | Potentiometer 0 wiper terminal, which can carry positive or negative current with voltage that must be between V+ and V-. |
| 13 | P0A | bidirectional | Potentiometer 0 Terminal A, the fixed connection to the full-scale wiper value (0xFF for 8-bit or 0x7F for 7-bit), which can carry positive or negative current with voltage between V+ and V-. |
| 14 | V+ | power_in | Analog positive supply voltage that must be higher than V-, with analog operating range of 10V to 36V for specified performance and a maximum of +36V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TSSOP-14 |
| Category | Data Acquisition |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Digital positive supply voltage (VL), with respect to DGND | VL | 2.7 |  | 5.5 | V | With respect to DGND | 4 |
| Digital positive supply voltage (VL), DGND referenced to V- | VL | 1.8 |  | 5.5 | V | DGND = V- + 0.9V (referenced to V-) | 4 |
| Analog positive supply voltage (V+) | V+ |  |  | 36 | V | With respect to V- | 4 |
| Resistor network supply voltage (VRN) | VRN |  |  | 36 | V | Delta voltage between V+ and V- | 4 |
| VL start voltage to ensure wiper reset | VDPOR |  |  | 1.8 | V | With respect to DGND, V+ > 6.0V | 4 |
| V+ voltage to ensure wiper reset | VAPOR |  |  | 6 | V | With respect to V-, VL = 0V | 4 |
| Power rail voltage during power-up, digital first | VLPOR |  |  | 5.5 | V | VL/DGND powers up first; V+ and V- floating or as V+/V- powers up | 4 |
| Power rail voltage during power-up, analog first | V+POR |  |  | 36 | V | Analog powers (V+/V-) up first; VL and DGND floating or as VL/DGND powers up | 4 |
| Delay after device exits the reset state (VL > VBOR) | TBORD |  | 10 | 20 | us | Delay after device exits the reset state (VL > VBOR) | 5 |
| Supply current, serial interface active | IDDD |  | 45 | 300 | uA | Serial interface active, write all 0s to volatile wiper 0; VL = 5.5V, CS = VIL, FSCK = 5 MHz, V- = DGND | 5 |
| Supply current, serial interface inactive | IDDD |  |  | 7 | uA | Serial interface inactive, VL = 5.5V, SCK = VIH, CS = VIH, Wiper = 0, V- = DGND | 5 |
| Supply current V+ to V- | IDDA |  |  | 5 | uA | Current V+ to V-, PxA = PxB = PxW, DGND = V- + (V+/2) | 5 |
| End-to-end resistance (RAB), 100 kOhm device | RAB | 80 | 100 | 120 | kΩ | -104 devices, V+/V- = 10V to 36V | 5 |
| RAB resistance tolerance | RAB | -20 |  | 20 | % | (± 20%) as printed on RAB row | 5 |
| RAB current | IAB |  |  | 0.45 | mA | -104 devices; 36V / RAB(MIN), V- = -18V, V+ = +18V | 5 |
| Wiper resistance RW | RW |  | 75 | 170 | Ω | IW = 1 mA, V+ = +18V, V- = -18V, code = 00h, PxA floating, PxB = V- | 6 |
| Wiper resistance RW at 5 V supply | RW |  | 145 | 200 | Ω | IW = 1 mA, V+ = +5.0V, V- = -5.0V, code = 00h, PxA floating, PxB = V- | 6 |
| Terminal current IT (A, B, W), 100 kOhm device | IT, IW |  |  | 6.5 | mA | -104 devices, IBW(W ≠ ZS) and IAW(W ≠ FS) | 6 |
| Terminal current at zero-scale or full-scale wiper | IT, IW |  |  | 36 | mA | IBW(W = ZS), or IAW(W = FS) | 6 |
| Nominal resistance temperature coefficient (RAB/T) | RAB/T |  | 50 |  | ppm/°C | TA = -40°C to +85°C | 6 |
| Nominal resistance temperature coefficient (RAB/T) | RAB/T |  | 100 |  | ppm/°C | TA = -40°C to +125°C | 6 |
| Ratiometric tempco (VWB/T) | VWB/T |  | 15 |  | ppm/°C | Code = Mid-scale (80h or 40h) | 6 |
| Input leakage current IIL | IIL | -1 |  | 1 | uA | VIN = VL and VIN = DGND | 13 |
| Power supply sensitivity (PSS), 8-bit | PSS |  | 0.0015 | 0.0035 | %/% | 8-bit, VL = 2.7V to 5.5V, V+ = 18V, V- = -18V, code = 7Fh | 14 |
| Full-scale error VWFSE, 100k 8-bit | VWFSE | -0.7 |  |  | LSb | 100k 8-bit, VAB = 20V to 36V | 7 |
| Full-scale error VWFSE, 100k 8-bit | VWFSE | -0.95 |  |  | LSb | 100k 8-bit, VAB = 10V to 36V | 7 |
| Zero-scale error VWZSE, 100k 8-bit | VWZSE |  |  | 0.5 | LSb | 100k 8-bit, VAB = 20V to 36V | 8 |
| Zero-scale error VWZSE, 100k 8-bit | VWZSE |  |  | 0.95 | LSb | 100k 8-bit, VAB = 10V to 36V | 8 |
| Zero-scale error VWZSE, 100k 8-bit | VWZSE |  |  | 0.7 | LSb | 100k 8-bit, VAB = 10V to 36V, -40°C ≤ TA ≤ +85°C | 8 |
| Potentiometer integral nonlinearity P-INL, 100k 8-bit | P-INL | -1.85 | 0.5 | 1.85 | LSb | 100k 8-bit, VAB = 10V to 36V | 9 |
| Potentiometer integral nonlinearity P-INL, 100k 8-bit | P-INL | -1.2 | 0.5 | 1.2 | LSb | 100k 8-bit, VAB = 20V to 36V | 9 |
| Potentiometer integral nonlinearity P-INL, 100k 8-bit | P-INL | -1 | 0.5 | 1 | LSb | 100k 8-bit, VAB = 10V to 36V, -40°C ≤ TA ≤ +85°C | 9 |
| Potentiometer differential nonlinearity P-DNL, 100k 8-bit | P-DNL | -0.25 | 0.125 | 0.25 | LSb | 100k 8-bit, VAB = 10V to 36V | 9 |
| Rheostat integral nonlinearity R-INL, 100k 8-bit | R-INL | -1 |  | 1 | LSb | 100k 8-bit, IW = 300 µA, (V+ - V-) = 36V | 11 |
| Rheostat integral nonlinearity R-INL, 100k 8-bit | R-INL | -1.2 |  | 1.2 | LSb | 100k 8-bit, IW = 83 µA, (V+ - V-) = 10V | 11 |
| Rheostat differential nonlinearity R-DNL, 100k 8-bit | R-DNL | -0.5 |  | 0.5 | LSb | 100k 8-bit, IW = 300 µA, (V+ - V-) = 36V | 12 |
| Voltage on V- with respect to DGND | V- | -40 |  |  | V | With respect to DGND; printed as DGND + 0.6V to -40.0V | 3 |
| Voltage on V+ with respect to DGND | V+ | -0.3 |  | 40 | V | With respect to DGND; printed as DGND - 0.3V to 40.0V | 3 |
| Voltage on VL with respect to DGND | VL | -0.6 |  | 7 | V | With respect to DGND | 3 |
| Voltage on CS, SCK, SDI, WLAT, SHDN with respect to DGND | VI | -0.6 |  |  | V | With respect to DGND; max is VL + 0.6V | 3 |
| Voltage on PxA, PxW, PxB with respect to V- | VPx | -0.3 |  |  | V | With respect to V-; max is V+ + 0.3V | 3 |
| Maximum continuous current into PxA, PxW, PxB, RAB = 100k | IPx | -6.5 |  | 6.5 | mA | Continuous, RAB = 100 k | 3 |
| Package power dissipation, TSSOP-14 | PD |  |  | 1000 | mW | TA = +50°C, TJ = +150°C | 3 |
| ESD protection, Human Body Model (HBM) | ESD | -4 |  | 4 | kV | Human body model, all pins | 3 |
| Maximum junction temperature | TJ |  |  | 150 | °C |  | 3 |
| Ambient temperature with power applied | TA | -40 |  | 125 | °C | With power applied | 3 |
| Storage temperature | TSTG | -65 |  | 150 | °C |  | 3 |
| Operating temperature range | TA | -40 |  | 125 | °C | Extended temperature range | 4 |
| Thermal resistance, junction to ambient, 14L-TSSOP | θJA |  | 100 |  | °C/W | 14L-TSSOP (ST) | 19 |
| SCK input frequency FSCK | FSCK |  |  | 10 | MHz | VL = 2.7V to 5.5V | 17 |
| SCK input frequency FSCK | FSCK |  |  | 1 | MHz | VL = 1.8V to 2.7V | 17 |
| SCK input high time | TscH | 35 |  |  | ns | VL = 2.7V to 5.5V | 17 |
| SCK input low time | TscL | 35 |  |  | ns | VL = 2.7V to 5.5V | 17 |
| SDO data output valid after SCK edge | TscL2DOV |  |  | 55 | ns | VL = 2.7V to 5.5V | 17 |
| CS inactive (VIH) after SCK edge | TscH2csI | 100 |  |  | ns |  | 17 |

## CAD (KiCad official)

- Symbol: `MCP41HV51-104E`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `mcp41hv51-104e-etched.step` / `mcp41hv51-104e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp41hv51-104e.step` / `mcp41hv51-104e.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588882322477629440) (92 pp, sha256 `06025745f8b9bc3f`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mcp41hv51-104e-datasheet.pdf)