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MCP4131-103E

Public Made by Adom

by adom

Microchip Tech Digital Potentiometers, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MCP4131-103E

Microchip Tech · Digital Potentiometers · PDIP-8

MCP4131-103E from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input SPI chip select input; forcing it to VIL enables serial commands and forcing it to VIHH enables high-voltage serial commands (high-voltage tolerant with Schmitt trigger).
2 SCK input SPI clock input, high-voltage tolerant with Schmitt trigger, up to 10 MHz in modes 0,0 and 1,1.
3 SDI/SDO bidirectional Multiplexed SPI serial data input/output on the MCP41X1; it drives read data after a valid Read command and its open-drain output uses the internal smart pull-up.
4 VSS power_in Ground reference for the device.
5 P0A passive Potentiometer 0 terminal A, the fixed full-scale connection of the wiper; voltage must be between VSS and VDD.
6 P0W passive Potentiometer 0 wiper terminal, the adjustable terminal; voltage must be between VSS and VDD.
7 P0B passive Potentiometer 0 terminal B, the fixed zero-scale connection of the wiper (wiper value 0x00); voltage must be between VSS and VDD.
8 VDD power_in Positive power supply input relative to VSS; device operates from 1.8V to 5.5V, with characteristics specified for 2.7V to 5.5V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package PDIP-8
Category ADC/DAC/Data Conversion
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD 2.7 5.5 V 4
Supply Voltage (serial interface only) VDD 1.8 2.7 V Serial Interface only 4
CS, SDI, SDO, SCK, SHDN pin voltage range VHV 12.5 V VDD ≥ 4.5V 4
Operating Temperature TA -40 125 °C Operating Temperature Range 14
Nominal resistance RAB (-103) RAB 8 10 12 kΩ -103 devices (Note 1) 5
Resistance tolerance RAB -20 20 % -103 devices 5
Wiper resistance RW 75 160 Ω VDD = 5.5 V, IW = 2.0 mA, code = 00h 5
Wiper resistance RW 75 300 Ω VDD = 2.7 V, IW = 2.0 mA, code = 00h 5
Maximum current through A, W or B IW 2.5 mA Note 6, worst case current through wiper when wiper is Full-Scale or Zero Scale 5
Resistor terminal input voltage range min VA,VW,VB 0 V VSS (lower limit); upper limit VDD; Note 5, Note 6 5
Supply current, serial interface active IDD 450 µA VDD = 5.5V, CS = VIL, SCK @ 5 MHz, write all 0's to volatile Wiper 0 4
Supply current, serial interface inactive IDD 2.5 5 µA CS = VIH, VDD = 5.5V 4
Supply current, active high-voltage command IDD 0.55 1 mA VDD = 5.5V, CS = VIHH, SCK @ 5 MHz, decrement volatile Wiper 0 4
VDD start voltage to ensure wiper reset VBOR 1.65 V RAM retention voltage (VRAM) < VBOR 4
Delay after device exits reset state TBORD 10 20 µs VDD > VBOR 4
Nominal resistance tempco ΔRAB/ΔT 50 ppm/°C TA = -20°C to +70°C 5
Nominal resistance tempco ΔRAB/ΔT 100 ppm/°C TA = -40°C to +85°C 5
Nominal resistance tempco ΔRAB/ΔT 150 ppm/°C TA = -40°C to +125°C 5
Ratiometric tempco ΔVWB/ΔT 15 ppm/°C Code = Midscale (80h or 40h) 5
Full-scale error, 10 kΩ 7-bit VWFSE -2 -0.1 LSb 10 kΩ 7-bit 3.0V ≤ VDD ≤ 5.5V 6
Zero-scale error, 10 kΩ 7-bit VWZSE 0.1 2 LSb 10 kΩ 7-bit 3.0V ≤ VDD ≤ 5.5V 6
Potentiometer integral non-linearity, 7-bit INL -0.5 0.25 0.5 LSb 7-bit, 3.0V ≤ VDD ≤ 5.5V, MCP4XX1 devices only (Note 2) 6
Potentiometer differential non-linearity, 7-bit DNL -0.25 0.125 0.25 LSb 7-bit, 3.0V ≤ VDD ≤ 5.5V, MCP4XX1 devices only (Note 2) 6
Rheostat INL, 10 kΩ 7-bit R-INL -1.125 0.5 1.125 LSb 10 kΩ 7-bit 5.5V, IW = 450 µA 7
Rheostat INL, 10 kΩ 7-bit R-INL -4 2.5 4 LSb 10 kΩ 7-bit 3.0V, IW = 240 µA (Note 7) 7
Rheostat DNL, 10 kΩ 7-bit R-DNL -0.375 0.25 0.375 LSb 10 kΩ 7-bit 5.5V, IW = 450 µA 8
Rheostat DNL, 10 kΩ 7-bit R-DNL -0.75 0.5 0.75 LSb 10 kΩ 7-bit 3.0V (Note 7) 8
Input leakage current IIL -1 1 µA VIN = VDD and VIN = VSS 9
High voltage limit VMAX 12.5 V Pin can tolerate VMAX or less (Note 6) 9
Weak pull-up/pull-down current IPU 1.75 mA Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VCS = 12.5V 9
SCK input frequency FSCK 10 MHz VDD = 2.7V to 5.5V 11
SCK input frequency FSCK 1 MHz VDD = 1.8V to 2.7V 11
CS active to SCK rising TcsA2scH 60 ns 11
SCK input high time TscH 45 ns VDD = 2.7V to 5.5V 11
SCK input low time TscL 45 ns VDD = 2.7V to 5.5V 11
SDI setup time to SCK rising TDIV2scH 10 ns 11
SDI hold time from SCK rising TscH2DIL 20 ns 11
CS inactive to SDO hi-impedance TcsH2DOZ 50 ns Note 1 11
SDO data output valid after SCK falling TscL2DOV 70 ns VDD = 2.7V to 5.5V 11
CS inactive after SCK rising TscH2csI 100 ns VDD = 2.7V to 5.5V 11
CS inactive hold to CS active TcsA2csI 50 ns 11
SCK input frequency (SDI/SDO multiplexed read) FSCK 250 kHz VDD = 2.7V to 5.5V 13
Bandwidth -3 dB, 10 kΩ 7-bit BW 1 MHz 10 kΩ 7-bit, Code = 40h, load = 30 pF 6
Capacitance (PA) CAW 75 pF f = 1 MHz, Code = Full-Scale 8
Capacitance (PW) CW 120 pF f = 1 MHz, Code = Full-Scale 8
Capacitance (PB) CBW 75 pF f = 1 MHz, Code = Full-Scale 8
Pin capacitance CIN, COUT 10 pF fC = 20 MHz 9
CS pull-up/pull-down resistance RCS 16 kΩ VDD = 5.5V, VCS = 3V 9
Voltage on VDD with respect to VSS VDD -0.6 7 V 3
Voltage on CS, SCK, SDI, SDI/SDO, SHDN with respect to VSS -0.6 12.5 V 3
Voltage on PxA, PxW, PxB, SDO with respect to VSS (lower limit) -0.3 V Upper limit VDD + 0.3V 3
Input clamp current IIK -20 20 mA VI < 0, VI > VDD, VI > VPP on HV pins 3
Output clamp current IOK -20 20 mA VO < 0 or VO > VDD 3
Maximum current into PxA, PxW & PxB pins -2.5 2.5 mA 3
Storage temperature -65 150 °C 3
Ambient temperature with power applied -40 125 °C 3
Maximum junction temperature TJ 150 °C 3
Soldering temperature of leads 300 °C 10 seconds 3
Thermal resistance, 8L-PDIP θJA 89.3 °C/W 14

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin P = Plastic Dual In-line (PDIP) (300 mil), 8/14-lead SN = Plastic Small Outline (SOIC), (150 mil), 8-lead 85

CAD (KiCad official)

  • Symbol: MCP4131-103E
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: PDIP-8 (KiCad packages3D, STEP)
  • 3D model files: mcp4131-103e-etched.step / mcp4131-103e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp4131-103e.step / mcp4131-103e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (88 pp, sha256 6c60b083b2ef0a92, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF