MCP41100-E from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CS	input	SPI chip select with Schmitt Trigger input, used to execute a new command after it has been loaded into the shift register.
2	SCK	input	SPI serial clock with Schmitt Trigger input, clocks data into SI on the rising edge and is gated by CS.
3	SI	input	SPI serial data input with Schmitt Trigger input, command and data bytes are clocked into the shift register and gated by CS.
4	VSS	power_in	Ground.
5	PA0	passive	Terminal A connection for potentiometer 0, disconnected from the resistor stack in shutdown.
6	PW0	passive	Wiper connection for potentiometer 0.
7	PB0	passive	Terminal B connection for potentiometer 0.
8	VDD	power_in	Positive supply for single-supply operation of 2.7V to 5.5V, with a 0.1 µF bypass capacitor recommended close to the pin.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	PDIP-8
Category	ADC/DAC/Data Conversion
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Nominal Resistance	R	70	100	130	kΩ	TA = +25°C (Note 1)	4
Rheostat Differential Non-Linearity	R-DNL	-1		1	LSB	Note 2	4
Rheostat Integral Non-Linearity	R-INL	-1		1	LSB	Note 2	4
Wiper Resistance	RW		125	175	Ω	VDD = 5.5V, IW = 1 mA, code 00h	4
Wiper Resistance	RW		175	250	Ω	VDD = 2.7V, IW = 1 mA, code 00h	4
Wiper Current	IW	-1		1	mA		4
Resolution	N	8			Bits		4
Monotonicity	N	8			Bits		4
Differential Non-Linearity	DNL	-1		1	LSB	Note 3	4
Integral Non-Linearity	INL	-1		1	LSB	Note 3	4
Full-Scale Error	VWFSE	-1	-0.25	0	LSB	Code FFh, VDD = 5V, see Figure 2-25	4
Full-Scale Error	VWFSE	-1	-0.35	0	LSB	Code FFh, VDD = 3V, see Figure 2-25	4
Zero-Scale Error	VWZSE	0	0.25	1	LSB	Code 00h, VDD = 5V, see Figure 2-25	4
Zero-Scale Error	VWZSE	0	0.35	1	LSB	Code 00h, VDD = 3V, see Figure 2-25	4
Resistor Terminal Voltage Range	VA,B,W	0			V	Note 4	4
Low-Level Output Voltage	VOL			0.4	V	IOL = 2.1 mA, VDD = 5V	4
Input Leakage Current	ILI	-1		1	µA	CS = VDD, VIN = VSS or VDD, includes VA SHDN=0	4
Operating Voltage Range	VDD	2.7		5.5	V		4
Supply Current, Active	IDDA		340	500	µA	VDD = 5.5V, CS = VSS, fSCK = 10 MHz, SO = Open, Code FFh (Note 6)	4
Supply Current, Static	IDDS		0.01	1	µA	CS, SHDN, RS = VDD = 5.5V, SO = Open (Note 6)	4
Power Supply Sensitivity	PSS		0.0015	0.0035	%/%	VDD = 4.5V - 5.5V, VA = 4.5V, Code 80h	4
Storage temperature		-60		150	°C		5
Ambient temp. with power applied		-60		125	°C		5
ESD protection on all pins		2			kV		5
Clock Frequency	FCLK			10	MHz	VDD = 5V (Note 1)	5
Clock High Time	tHI	40			ns		5
Clock Low Time	tLO	40			ns		5
CS Fall to First Rising CLK Edge	tCSSR	40			ns		5
Data Input Setup Time	tSU	40			ns		5
Data Input Hold Time	tHD	10			ns		5
SCK Fall to SO Valid Propagation Delay	tDO			80	ns	CL = 30 pF (Note 2)	5
SCK Rise to CS Rise Hold Time	tCHS	30			ns		5
SCK Rise to CS Fall Delay	tCS0	10			ns		5
CS Rise to CLK Rise Hold	tCS1	100			ns		5
CS High Time	tCSH	40			ns		5
Rheostat Tempco	∆RAB/∆T		800		ppm/°C		4
Voltage Divider Tempco	∆VW/∆T		1		ppm/°C	Code 80h	4
Capacitance (CA or CB)			11		pF	f =1 MHz, Code = 80h, see Figure 2-30	4
Capacitance CW	CW		5.6		pF	f =1 MHz, Code = 80h, see Figure 2-30	4
Bandwidth -3dB	BW		145		MHz	VB = 0V, Measured at Code 80h, Output Load = 30 PF	4
Settling Time	tS		18		µS	VA = VDD,VB = 0V, ±1% Error Band, Transition from Code 00h to Code 80h, Output Load = 30 pF	4
Resistor Noise Voltage	eNWB		29		nV/√Hz	VA = Open, Code 80h, f =1 kHz	4
Crosstalk	CT		-95		dB	VA = VDD, VB = 0V (Note 5)	4
Pin Capacitance (All inputs/outputs)	CIN, COUT		10		pF	VDD = 5.0V, TA = +25°C, fc = 1 MHz	4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	8-Lead Plastic Small Outline (SN), Narrow, 150 mil (SOIC) Foot Angle φ 048048	25

CAD (KiCad official)

Symbol: MCP41100-E
Footprint: Package_DIP:DIP-8_W7.62mm
3D model: PDIP-8 (KiCad packages3D, STEP)
3D model files: mcp41100-e-etched.step / mcp41100-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp41100-e.step / mcp41100-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (32 pp, sha256 6bee8156c8b9f1f6, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

MCP41100-E

Verified MCP41100-E

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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