component
MCP4019T-103E
Public Made by Adomby adom
Microchip Tech Digital Potentiometers, SC-70-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MCP4019T-103E
Microchip Tech · Digital Potentiometers · SC-70-5
MCP4019T-103E from Microchip Tech, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive power supply input, ranging from 1.8V to 5.5V relative to VSS; a decoupling capacitor to VSS is recommended. |
| 2 | VSS | power_in | Ground reference for the device. |
| 3 | SCL | input | I2C serial clock pin (Schmitt trigger, open drain); the device acts only as a slave and accepts only external serial clocks. |
| 4 | SDA | bidirectional | I2C serial data pin with Schmitt trigger input and open-drain output. |
| 5 | W | passive | Potentiometer wiper terminal, adjustable, supports positive and negative current, and its voltage must be between VSS and VDD. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SC-70-5 |
| Category | ADC/DAC/Data Conversion |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (analog characteristics specified) | VDD | 2.7 | 5.5 | V | Analog Characteristics specified | 4 | |
| Supply voltage (digital characteristics specified) | VDD | 1.8 | 5.5 | V | Digital Characteristics specified | 4 | |
| VDD start voltage to ensure wiper reset | VBOR | 1.65 | V | RAM retention voltage (VRAM) < VBOR | 4 | ||
| Delay after device exits reset state | TBORD | 10 | 20 | µS | VDD > VBOR | 4 | |
| Supply current, interface active | IDD | 45 | 80 | µA | Serial Interface Active, Write all 0's to Volatile Wiper, VDD = 5.5V, FSCL = 400 kHz | 4 | |
| Supply current, interface inactive | IDD | 2.5 | 5 | µA | Serial Interface Inactive (Stop condition, SCL = SDA = VIH), Wiper = 0, VDD = 5.5V | 4 | |
| Nominal resistance (-103 device) | RAB | 8 | 10 | 12 | kΩ | -103 devices (Note 1) | 5 |
| Resistance tolerance | RAB | -20 | 20 | % | Resistance (± 20%) | 5 | |
| Wiper resistance at 5.5V | RW | 100 | 170 | Ω | VDD = 5.5 V, IW = 2.0 mA, code = 00h | 5 | |
| Wiper resistance at 2.7V | RW | 155 | 325 | Ω | VDD = 2.7 V, IW = 2.0 mA, code = 00h | 5 | |
| Max current through terminal A | IT | 2.5 | mA | Terminal A IAW, W = Full Scale (FS) | 5 | ||
| Max current through terminal B | IT | 2.5 | mA | Terminal B IBW, W = Zero Scale (ZS) | 5 | ||
| Max current through terminal W | IT | 2.5 | mA | Terminal W IAW or IBW, W = FS or ZS | 5 | ||
| Max current between A and B | IAB | 0.688 | mA | IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 8000 | 5 | ||
| Rheostat INL, 5.5V | R-INL | -2 | 0.5 | 2 | LSb | 10 kΩ 5.5V, IW = 450 µA | 7 |
| Rheostat INL, 2.7V | R-INL | -4 | 2.5 | 4 | LSb | 10 kΩ 2.7V, IW = 215 µA (Note 6) | 7 |
| Rheostat DNL, 5.5V | R-DNL | -0.5 | 0.25 | 0.5 | LSb | 10 kΩ 5.5V, IW = 450 µA | 7 |
| Rheostat DNL, 2.7V | R-DNL | -0.75 | 0.5 | 0.75 | LSb | 10 kΩ 2.7V, IW = 215 µA (Note 6) | 7 |
| Input low threshold (minimum) | VIL | -0.5 | V | Schmitt Trigger Low Input Threshold; max is 0.3VDD | 8 | ||
| Output low voltage (SDA) | VOL | 0.4 | V | VDD ≥ 2.0V, IOL = 3 mA | 8 | ||
| Input leakage current | IIL | -1 | 1 | µA | VIN = VDD and VIN = VSS | 8 | |
| Power supply sensitivity (MCP4018 only) | PSS | 0.0005 | 0.0035 | %/% | VDD = 2.7V to 5.5V, VA = 2.7V, Code = 3Fh | 8 | |
| Absolute max VDD | VDD | -0.6 | 7 | V | Voltage on VDD with respect to VSS | 3 | |
| Absolute max voltage on SCL and SDA | -0.6 | 12.5 | V | with respect to VSS | 3 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0, VI > VDD, VI > VPP ON HV pins | 3 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VDD | 3 | |
| Max output current sunk by any output pin | 25 | mA | 3 | ||||
| Max output current sourced by any output pin | 25 | mA | 3 | ||||
| Max current out of VSS pin | 100 | mA | 3 | ||||
| Max current into VDD pin | 100 | mA | 3 | ||||
| Max current into A, W and B pins | -2.5 | 2.5 | mA | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Ambient temperature with power applied | -40 | 125 | °C | 3 | |||
| Maximum junction temperature | TJ | 150 | °C | 3 | |||
| ESD protection HBM | 4 | kV | all pins, HBM | 3 | |||
| Operating temperature range | TA | -40 | 125 | °C | 11 | ||
| Thermal resistance 5L-SC70 | θJA | 331 | °C/W | 11 | |||
| Nominal resistance tempco | ΔRAB/ΔT | 50 | ppm/°C | TA = -20°C to +70°C | 5 | ||
| Nominal resistance tempco | ΔRAB/ΔT | 100 | ppm/°C | TA = -40°C to +85°C | 5 | ||
| Nominal resistance tempco | ΔRAB/ΔT | 150 | ppm/°C | TA = -40°C to +125°C | 5 | ||
| Ratiometric tempco | ΔVWB/ΔT | 15 | ppm/°C | Code = Midscale (3Fh) | 5 | ||
| Bandwidth -3 dB | BW | 1 | MHz | 10 kΩ Code = 3Fh, load = 30 pF | 6 | ||
| Capacitance (PA) | CAW | 75 | pF | f =1 MHz, Code = Full Scale | 7 | ||
| Capacitance (PW) | CW | 120 | pF | f =1 MHz, Code = Full Scale | 7 | ||
| Capacitance (PB) | CBW | 75 | pF | f =1 MHz, Code = Full Scale | 7 | ||
| Pin capacitance | CIN, COUT | 10 | pF | fC = 400 kHz | 8 | ||
| SCL clock frequency, fast mode | FSCL | 0 | 400 | kHz | Cb = 400 pF, 2.7V - 5.5V | 9 | |
| SCL clock frequency, standard mode | FSCL | 0 | 100 | kHz | Cb = 400 pF, 1.8V - 5.5V | 9 | |
| Clock high time, 400 kHz mode | THIGH | 600 | ns | 2.7V-5.5V | 10 | ||
| Clock low time, 400 kHz mode | TLOW | 1300 | ns | 2.7V-5.5V | 10 | ||
| Data input setup time, 400 kHz mode | TSU:DAT | 100 | ns | 10 | |||
| Output valid from clock, 400 kHz mode | TAA | 900 | ns | 10 | |||
| Bus free time, 400 kHz mode | TBUF | 1300 | ns | 10 |
CAD (KiCad official)
- Symbol:
MCP4019T-103E - Footprint:
Package_TO_SOT_SMD:SOT-353_SC-70-5 - 3D model: SC-70-5 (KiCad packages3D, STEP)
- 3D model files:
mcp4019t-103e-etched.step/mcp4019t-103e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4019t-103e.step/mcp4019t-103e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (66 pp, sha256
639a6adea91aa644, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP4019T-103E
**Microchip Tech** · Digital Potentiometers · SC-70-5
MCP4019T-103E from Microchip Tech, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive power supply input, ranging from 1.8V to 5.5V relative to VSS; a decoupling capacitor to VSS is recommended. |
| 2 | VSS | power_in | Ground reference for the device. |
| 3 | SCL | input | I2C serial clock pin (Schmitt trigger, open drain); the device acts only as a slave and accepts only external serial clocks. |
| 4 | SDA | bidirectional | I2C serial data pin with Schmitt trigger input and open-drain output. |
| 5 | W | passive | Potentiometer wiper terminal, adjustable, supports positive and negative current, and its voltage must be between VSS and VDD. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SC-70-5 |
| Category | ADC/DAC/Data Conversion |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (analog characteristics specified) | VDD | 2.7 | | 5.5 | V | Analog Characteristics specified | 4 |
| Supply voltage (digital characteristics specified) | VDD | 1.8 | | 5.5 | V | Digital Characteristics specified | 4 |
| VDD start voltage to ensure wiper reset | VBOR | | | 1.65 | V | RAM retention voltage (VRAM) < VBOR | 4 |
| Delay after device exits reset state | TBORD | | 10 | 20 | µS | VDD > VBOR | 4 |
| Supply current, interface active | IDD | | 45 | 80 | µA | Serial Interface Active, Write all 0's to Volatile Wiper, VDD = 5.5V, FSCL = 400 kHz | 4 |
| Supply current, interface inactive | IDD | | 2.5 | 5 | µA | Serial Interface Inactive (Stop condition, SCL = SDA = VIH), Wiper = 0, VDD = 5.5V | 4 |
| Nominal resistance (-103 device) | RAB | 8 | 10 | 12 | kΩ | -103 devices (Note 1) | 5 |
| Resistance tolerance | RAB | -20 | | 20 | % | Resistance (± 20%) | 5 |
| Wiper resistance at 5.5V | RW | | 100 | 170 | Ω | VDD = 5.5 V, IW = 2.0 mA, code = 00h | 5 |
| Wiper resistance at 2.7V | RW | | 155 | 325 | Ω | VDD = 2.7 V, IW = 2.0 mA, code = 00h | 5 |
| Max current through terminal A | IT | | | 2.5 | mA | Terminal A IAW, W = Full Scale (FS) | 5 |
| Max current through terminal B | IT | | | 2.5 | mA | Terminal B IBW, W = Zero Scale (ZS) | 5 |
| Max current through terminal W | IT | | | 2.5 | mA | Terminal W IAW or IBW, W = FS or ZS | 5 |
| Max current between A and B | IAB | | | 0.688 | mA | IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 8000 | 5 |
| Rheostat INL, 5.5V | R-INL | -2 | 0.5 | 2 | LSb | 10 kΩ 5.5V, IW = 450 µA | 7 |
| Rheostat INL, 2.7V | R-INL | -4 | 2.5 | 4 | LSb | 10 kΩ 2.7V, IW = 215 µA (Note 6) | 7 |
| Rheostat DNL, 5.5V | R-DNL | -0.5 | 0.25 | 0.5 | LSb | 10 kΩ 5.5V, IW = 450 µA | 7 |
| Rheostat DNL, 2.7V | R-DNL | -0.75 | 0.5 | 0.75 | LSb | 10 kΩ 2.7V, IW = 215 µA (Note 6) | 7 |
| Input low threshold (minimum) | VIL | -0.5 | | | V | Schmitt Trigger Low Input Threshold; max is 0.3VDD | 8 |
| Output low voltage (SDA) | VOL | | | 0.4 | V | VDD ≥ 2.0V, IOL = 3 mA | 8 |
| Input leakage current | IIL | -1 | | 1 | µA | VIN = VDD and VIN = VSS | 8 |
| Power supply sensitivity (MCP4018 only) | PSS | | 0.0005 | 0.0035 | %/% | VDD = 2.7V to 5.5V, VA = 2.7V, Code = 3Fh | 8 |
| Absolute max VDD | VDD | -0.6 | | 7 | V | Voltage on VDD with respect to VSS | 3 |
| Absolute max voltage on SCL and SDA | | -0.6 | | 12.5 | V | with respect to VSS | 3 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < 0, VI > VDD, VI > VPP ON HV pins | 3 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < 0 or VO > VDD | 3 |
| Max output current sunk by any output pin | | | | 25 | mA | | 3 |
| Max output current sourced by any output pin | | | | 25 | mA | | 3 |
| Max current out of VSS pin | | | | 100 | mA | | 3 |
| Max current into VDD pin | | | | 100 | mA | | 3 |
| Max current into A, W and B pins | | -2.5 | | 2.5 | mA | | 3 |
| Storage temperature | | -65 | | 150 | °C | | 3 |
| Ambient temperature with power applied | | -40 | | 125 | °C | | 3 |
| Maximum junction temperature | TJ | | | 150 | °C | | 3 |
| ESD protection HBM | | 4 | | | kV | all pins, HBM | 3 |
| Operating temperature range | TA | -40 | | 125 | °C | | 11 |
| Thermal resistance 5L-SC70 | θJA | | 331 | | °C/W | | 11 |
| Nominal resistance tempco | ΔRAB/ΔT | | 50 | | ppm/°C | TA = -20°C to +70°C | 5 |
| Nominal resistance tempco | ΔRAB/ΔT | | 100 | | ppm/°C | TA = -40°C to +85°C | 5 |
| Nominal resistance tempco | ΔRAB/ΔT | | 150 | | ppm/°C | TA = -40°C to +125°C | 5 |
| Ratiometric tempco | ΔVWB/ΔT | | 15 | | ppm/°C | Code = Midscale (3Fh) | 5 |
| Bandwidth -3 dB | BW | | 1 | | MHz | 10 kΩ Code = 3Fh, load = 30 pF | 6 |
| Capacitance (PA) | CAW | | 75 | | pF | f =1 MHz, Code = Full Scale | 7 |
| Capacitance (PW) | CW | | 120 | | pF | f =1 MHz, Code = Full Scale | 7 |
| Capacitance (PB) | CBW | | 75 | | pF | f =1 MHz, Code = Full Scale | 7 |
| Pin capacitance | CIN, COUT | | 10 | | pF | fC = 400 kHz | 8 |
| SCL clock frequency, fast mode | FSCL | 0 | | 400 | kHz | Cb = 400 pF, 2.7V - 5.5V | 9 |
| SCL clock frequency, standard mode | FSCL | 0 | | 100 | kHz | Cb = 400 pF, 1.8V - 5.5V | 9 |
| Clock high time, 400 kHz mode | THIGH | 600 | | | ns | 2.7V-5.5V | 10 |
| Clock low time, 400 kHz mode | TLOW | 1300 | | | ns | 2.7V-5.5V | 10 |
| Data input setup time, 400 kHz mode | TSU:DAT | 100 | | | ns | | 10 |
| Output valid from clock, 400 kHz mode | TAA | | | 900 | ns | | 10 |
| Bus free time, 400 kHz mode | TBUF | 1300 | | | ns | | 10 |
## CAD (KiCad official)
- Symbol: `MCP4019T-103E`
- Footprint: `Package_TO_SOT_SMD:SOT-353_SC-70-5`
- 3D model: SC-70-5 (KiCad packages3D, STEP)
- 3D model files: `mcp4019t-103e-etched.step` / `mcp4019t-103e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp4019t-103e.step` / `mcp4019t-103e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://ww1.microchip.com/downloads/en/DeviceDoc/22147a.pdf) (66 pp, sha256 `639a6adea91aa644`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp4019t-103e-datasheet.pdf)