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MCP3914A1-E

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Microchip Tech Analog Front End (AFE), QFN-40-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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MCP3914A1-E

Microchip Tech · Analog Front End (AFE) · QFN-40-EP(5x5)

MCP3914A1-E from Microchip Tech, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CH2+ input Non-inverting differential input for Channel 2, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
2 CH2- input Inverting differential input for Channel 2, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
3 CH3- input Inverting differential input for Channel 3, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
4 CH3+ input Non-inverting differential input for Channel 3, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
5 NC unconnected No Connect.
6 NC unconnected No Connect.
7 CH4+ input Non-inverting differential input for Channel 4, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
8 CH4- input Inverting differential input for Channel 4, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
9 CH5- input Inverting differential input for Channel 5, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
10 CH5+ input Non-inverting differential input for Channel 5, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
11 CH6+ input Non-inverting differential input for Channel 6, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
12 CH6- input Inverting differential input for Channel 6, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
13 CH7- input Inverting differential input for Channel 7, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
14 CH7+ input Non-inverting differential input for Channel 7, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
15 REFIN+/OUT bidirectional Non-inverting reference input or internal 1.2V reference output (±2% tolerance, 9 ppm/°C tempco), 10 pF input capacitance, selected by VREFEXT bit.
16 REFIN- input Inverting reference input or ground connection for single-ended reference; must be connected to AGND when using internal reference or single-ended external reference.
17 AGND power_in Analog ground return path for internal analog circuitry; must be connected for proper device operation, star connection recommended.
18 AVDD power_in Analog power supply pin, 2.7V to 3.6V operating range with 10 µF and 0.1 µF decoupling capacitors required.
19 NC unconnected No Connect.
20 DVDD power_in Digital power supply pin, 2.7V to 3.6V operating range with 10 µF and 0.1 µF decoupling capacitors required.
21 DGND power_in Digital ground return path for internal digital circuitry; must be connected for proper device operation, star connection recommended.
22 DR output Data Ready output signal, active-low pulse with width equal to half DMCLK period, indicates new conversion result ready for reading.
23 NC unconnected No Connect.
24 DGND power_in Digital ground return path for internal digital circuitry; must be connected for proper device operation, star connection recommended.
25 OSC1/CLKI input Oscillator crystal connection or external clock input (1 to 20 MHz), selected by CLKEXT bit; must provide master clock for ADC operation.
26 OSC2 passive Oscillator crystal connection pin for resonant crystal with proper load capacitance; must be connected to DGND when using external clock (CLKEXT=1) with internal pull-down.
27 CS input Serial Interface Chip Select input, active low; falling edge initiates communication, rising edge terminates, Schmitt-triggered.
28 SCK input Serial clock input, maximum 20 MHz, data clocked in on rising edge and out on falling edge, Schmitt-triggered, compatible with SPI modes 0,0 and 1,1.
29 SDO tri_state Serial data output, high-impedance during command byte and write operations, maximum output frequency 20 MHz.
30 SDI input Serial data input for 8-bit commands, data clocked in on rising edge of SCK, 100 kΩ pull-up to DVDD recommended when DR_HIZ bit is low, Schmitt-triggered.
31 RESET input Master Reset input, active low, Schmitt-triggered; minimum 100 ns pulse width required, resets all registers to default power-on state.
32 DGND power_in Digital ground return path for internal digital circuitry; must be connected for proper device operation, star connection recommended.
33 DVDD power_in Digital power supply pin, 2.7V to 3.6V operating range with 10 µF and 0.1 µF decoupling capacitors required.
34 NC unconnected No Connect.
35 AVDD power_in Analog power supply pin, 2.7V to 3.6V operating range with 10 µF and 0.1 µF decoupling capacitors required.
36 AGND power_in Analog ground return path for internal analog circuitry; must be connected for proper device operation, star connection recommended.
37 CH0+ input Non-inverting differential input for Channel 0, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
38 CH0- input Inverting differential input for Channel 0, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
39 CH1- input Inverting differential input for Channel 1, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
40 CH1+ input Non-inverting differential input for Channel 1, ±600 mV/GAIN differential range and ±1 V absolute range to AGND, 232 kΩ input impedance at gain 1.
41 EP passive Exposed thermal pad for heat dissipation, must be connected to AGND for optimal thermal performance or left floating.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-40-EP(5x5)
Category Data Acquisition
Pins 41

CAD (KiCad official)

  • Symbol: MCP3914A1-E
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: mcp3914a1-e-etched.step / mcp3914a1-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp3914a1-e.step / mcp3914a1-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (80 pp, sha256 ad1e415765f2a026, retrieved 2026-09-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF