# MCP3550-60E

**Microchip Tech** · Analog To Digital Converters (ADCs) · SOIC-8

MCP3550-60E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Reference voltage analog input accepting single-ended reference voltages from 0.1V to VDD. |
| 2 | VIN+ | power_in | Non-inverting analog input; absolute voltage range extends from VSS - 0.3V to VDD + 0.3V. |
| 3 | VIN- | power_in | Inverting analog input; absolute voltage range extends from VSS - 0.3V to VDD + 0.3V. |
| 4 | VSS | power_in | Ground pin and current return path for analog and digital circuitry. |
| 5 | SCK | input | Serial clock digital input that synchronizes data communication, supporting SPI mode 1,1 and 0,0, with data shifted out on the falling edge. |
| 6 | SDO/RDY | output | Data/ready digital output that goes active-low when a conversion is complete and then shifts out the 24-bit data word on falling SCK edges, high-impedance when CS is high. |
| 7 | CS | input | Chip select digital input that gates communication and starts conversions on its falling edge; may be tied low for two-wire continuous conversion mode. |
| 8 | VDD | power_in | Positive supply voltage pin for analog and digital circuitry, 2.7V to 5.5V with a 0.1 µF bypass capacitor. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Conversion Time | tCONV | -2 | 66.67 | 2 | ms | MCP3550-60 (min/max printed as % of typ) | 3 |
| No Missing Codes | NMC | 22 |  |  | bits | At DC (Note 5) | 3 |
| Integral Non-Linearity | INL |  | 2 | 6 | ppm | TA = +25°C only (Note 2) | 3 |
| Offset Error | VOS | -12 | 3 | 12 | µV | TA = +25°C | 3 |
| Positive Full-Scale Error | VFS,P | -10 | 2 | 10 | ppm | TA = +25°C only | 3 |
| Negative Full-Scale Error | VFS,N | -10 | 2 | 10 | ppm | TA = +25°C only | 3 |
| Power Supply Voltage Range | VDD | 2.7 |  | 5.5 | V |  | 4 |
| Supply Current (MCP3550-60) | IDD |  | 140 | 185 | µA | VDD = 5V | 4 |
| Supply Current (MCP3550-60) | IDD |  | 120 |  | µA | VDD = 2.7V | 4 |
| Supply Current, Shutdown Mode | IDDS |  |  | 1 | µA | CS = SCK = VDD | 4 |
| Voltage Input High (CS, SCK) | VIH | 0.7 |  |  | V | min printed as 0.7 VDD | 4 |
| Voltage Input Low (CS, SCK) | VIL |  |  | 0.4 | V |  | 4 |
| Voltage Output High (SDO/RDY) | VOH | -0.5 |  |  | V | VOH = 1 mA, VDD = 5.0V; min printed as VDD - 0.5 | 4 |
| Voltage Output Low (SDO/RDY) | VOL |  |  | 0.4 | V | VOH = -1 mA, VDD = 5.0V | 5 |
| Input leakage Current (CS, SCK) | ILI | -1 |  | 1 | µA |  | 5 |
| CLK Frequency | fSCK |  |  | 5 | MHz | VDD = 3.3V or 5.0V, SDO load = 50 pF | 5 |
| CLK High | tHI | 90 |  |  | ns |  | 5 |
| CLK Low | tLO | 90 |  |  | ns |  | 5 |
| CLK fall to output data valid | tDO | 0 |  | 90 | ns |  | 5 |
| CS low to indicate RDY state | tRDY | 0 |  | 50 | ns |  | 5 |
| CS minimum low time | tCSL | 8 |  |  | µs | Note | 5 |
| RDY flag setup time | tSU | 20 |  |  | ns |  | 5 |
| CS rise to output disable | tDIS | 20 |  |  | ns |  | 5 |
| CS disable time | tCSD | 90 |  |  | ns |  | 5 |
| Specified Temperature Range | TA | -40 |  | 85 | °C |  | 5 |
| Operating Temperature Range | TA | -40 |  | 125 | °C |  | 5 |
| Thermal Resistance, 8L-SOIC | θJA |  | 149.5 |  | °C/W |  | 5 |
| Input/Output Voltage w.r.t VSS |  | -0.3 |  | 0.3 | V | -0.3V to VDD + 0.3V (max printed as VDD + 0.3V) | 3 |
| Current at Input Pins |  | -2 |  | 2 | mA |  | 3 |
| Current at Output and Supply Pins |  | -10 |  | 10 | mA |  | 3 |
| Storage Temperature |  | -65 |  | 150 | °C |  | 3 |
| Ambient temp. with power applied |  | -55 |  | 125 | °C |  | 3 |
| Maximum Junction Temperature | TJ |  |  | 150 | °C |  | 3 |
| Output Noise | eN |  | 2.5 |  | µVRMS |  | 3 |
| Effective Resolution | ER |  | 21.9 |  | bits RMS | VREF = 5V | 3 |
| Offset Drift |  |  | 0.04 |  | ppm/°C |  | 3 |
| Positive/Negative Full-Scale Error Drift |  |  | 0.028 |  | ppm/°C |  | 3 |
| Power Supply 50/60 Hz Rejection | PSRR |  | -120 |  | dB | MCP3550-50 or MCP3550-60 only at 50 or 60 Hz respectively, VDD varies from 4.5V to 5.5V | 4 |
| Normal Mode 50 or 60 Hz Rejection | NMRR |  | -120 |  | dB | MCP3550-50 or MCP3550-60 only at 50 or 60 Hz respectively, 0 < VCM < VDD, -VREF < VIN < +VREF | 4 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | Package: MS = Plastic MSOP, 8-lead SN = Plastic SOIC (150 mil Body), 8-lead | 37 |

## CAD (KiCad official)

- Symbol: `MCP3550-60E`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `mcp3550-60e-etched.step` / `mcp3550-60e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp3550-60e.step` / `mcp3550-60e.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/mcp3550-60e-datasheet.pdf) (40 pp, sha256 `87917c931a7d2bf4`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mcp3550-60e-datasheet.pdf)