component
MCP3550
Public Made by Adomby adom
Microchip 22-bit low-power delta-sigma ADC, MSOP-8. SPI, single differential input, on-chip 50/60 Hz rejection. Datasheet-verified.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMCP3550
Microchip · Delta-sigma ADC · MSOP-8
Single-channel 22-bit delta-sigma ADC that reads one differential input and returns the result over SPI, drawing only about 120 uA. On-chip digital filtering rejects 50 Hz or 60 Hz line noise (part option), so it suits weigh scales and slow precision sensors on mains-powered gear. It uses an external reference at VREF and outputs a ready flag on SDO. A compact, low-power converter where resolution matters more than speed.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | input | Reference voltage analog input. Accepts a single-ended reference from 0.1 V to VDD; sets the full-scale conversion range (2*VREF differential). Lower VREF reduces INL error (which scales with VREF^2) but does not significantly reduce output noise. |
| 2 | VIN+ | input | Non-inverting analog input of the differential ADC. Together with VIN-, forms the fully differential measurement input; ensured accuracy from -VREF to +VREF with about 12% overrange available at room temperature. |
| 3 | VIN- | input | Inverting analog input of the differential ADC. Absolute voltage on VIN+/VIN- must remain within VSS-0.3 V to VDD+0.3 V; exceeding this range activates ESD diode leakage and degrades performance. |
| 4 | VSS | power_in | Ground return for both analog and digital circuitry. Should be tied to the analog ground plane of the PCB when one is available. |
| 5 | SCK | input | Serial clock digital input. Synchronizes data shifted out on SDO on the falling edge; input is latched on the rising edge. Supports SPI modes 0,0 and 1,1 up to 5 MHz; may idle high or low while CS is high. VIH = 0.7*VDD, VIL = 0.4 V. |
| 6 | SDO/RDY | output | Serial data output / ready flag. Goes active-low when a conversion completes to signal ready; subsequent SCK falling edges then shift out a 24-bit word (2 overflow bits + 22 data bits). Enters high-impedance when CS is high. VOH >= VDD-0.5 V, VOL <= 0.4 V at 1 mA. |
| 7 | CS | input | Active-low chip select. Gates all SPI communication and controls internal conversions - a conversion begins on the falling edge of CS. Raising CS before conversion completes selects Single-Conversion mode; leaving CS low selects Continuous-Conversion mode and may be tied permanently low for 2-wire operation. |
| 8 | VDD | power_in | Positive supply, 2.7-5.5 V. Requires a 0.1 uF bypass capacitor. Typical IDD is 100-140 uA depending on part/VDD; sleep/shutdown current is ~1-10 uA. |
Key specifications
| Parameter | Value |
|---|---|
| Type | 22-bit delta-sigma ADC |
| Channels | 1 differential |
| Interface | SPI |
| Line rejection | 50 Hz or 60 Hz (part option) |
| Supply current | 120 uA (typ) |
| Reference | External (VREF) |
| Supply | 2.7-5.5 V |
| Package | MSOP-8 |
Ordering variants
Same part, different packaging or reel option.
MCP3550-50E/MS (60 Hz reject, MSOP-8)MCP3550-60E/MS (50 Hz reject, MSOP-8)MCP3551E/MS (fast settle)
CAD (KiCad official)
- Symbol:
Analog_ADC:MCP3550-50-EMS (KiCad official) - Footprint:
Package_SO:MSOP-8_3x3mm_P0.65mm - 3D model: MSOP-8 (KiCad packages3D, STEP)
- 3D model files:
mcp3550-etched.step/mcp3550-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp3550.step/mcp3550.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip datasheet (40 pp, sha256
87917c931a7d2bf4, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).