MCP3426A1-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CH1+	input	Positive differential analog input of channel 1, with a usable range of VSS-0.3V to VDD+0.3V.
2	CH1-	input	Negative differential analog input of channel 1, which can be tied to VSS for single-ended operation, with a range of VSS-0.3V to VDD+0.3V.
3	VDD	power_in	Positive supply pin, specified for 2.7V to 5.5V, with a bypass of about 0.1 µF ceramic to ground plus a recommended 10 µF tantalum in parallel.
4	SDA	bidirectional	Bidirectional open-drain serial data pin of the I2C interface that needs a pull-up resistor to VDD (5 kΩ to 10 kΩ for standard and fast modes, under 1 kΩ for high-speed mode).
5	SCL	input	Serial clock pin of the I2C interface (slave only, open-drain N-channel) that needs a pull-up resistor to VDD.
6	VSS	power_in	Ground pin and current return path, to be connected to a ground plane (preferably analog ground) through a low-impedance connection.
7	CH2+	input	Positive differential analog input of channel 2, with a usable range of VSS-0.3V to VDD+0.3V.
8	CH2-	input	Negative differential analog input of channel 2, which can be tied to VSS for single-ended operation, with a range of VSS-0.3V to VDD+0.3V.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	SOIC-8
Category	ADC/DAC/Data Conversion
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage Absolute Maximum	VDD			7	V		5
All inputs and outputs voltage		-0.4		0.4	V	VSS -0.4V to VDD+0.4V (relative to VSS/VDD)	5
Current at Input Pins		-2		2	mA		5
Current at Output and Supply Pins		-10		10	mA		5
Storage Temperature		-65		150	°C		5
Ambient Temp. with power applied		-55		125	°C		5
Maximum Junction Temperature	TJ			150	°C		5
Maximum Input Voltage Range		-0.3		0.3	V	VSS-0.3 to VDD+0.3 (Note 1)	5
Resolution and No Missing Codes		12			Bits	DR = 240 SPS	5
Resolution and No Missing Codes		14			Bits	DR = 60 SPS	5
Resolution and No Missing Codes		16			Bits	DR = 15 SPS	5
Data Rate	DR	176	240	328	SPS	12 bits mode	5
Data Rate	DR	44	60	82	SPS	14 bits mode	5
Data Rate	DR	11	15	20.5	SPS	16 bits mode	5
Supply Voltage Range	VDD	2.7		5.5	V		6
Supply Current during Conversion	IDDA		145	180	µA	VDD = 5.0V	6
Supply Current during Conversion	IDDA		135		µA	VDD = 3.0V	6
Supply Current during Standby Mode	IDDS		0.3	1	µA	VDD = 5.0V	6
High level input voltage	VIH	0.7		1	V	at SDA and SCL pins; 0.7VDD to VDD (multiples of VDD)	6
Low level input voltage	VIL			0.3	V	at SDA and SCL pins; 0.3VDD	6
Low level output voltage	VOL			0.4	V	IOL = 3 mA	6
Hysteresis of Schmidt Trigger for inputs	VHYST	0.05			V	0.05VDD; fSCL = 100 kHz	6
Supply Current when I2C bus line is active	IDDB			10	µA	Device is in standby mode while I2C bus is active	6
Input Leakage Current	IILH			1	µA	VIH = 5.5V	6
Input Leakage Current	IILL	-1			µA	VIL = GND	6
Pin capacitance	CPIN		4	10	pF		6
I2C Bus Capacitance	Cb			400	pF		6
Specified Temperature Range	TA	-40		85	°C		7
Operating Temperature Range	TA	-40		125	°C		7
Thermal Resistance, 8L-SOIC	θJA		149.5		°C/W		7
Differential Input Impedance	ZIND		2.25		MΩ	2.25/PGA; during normal mode operation	5
Common Mode input Impedance	ZINC		25		MΩ	PGA = 1, 2, 4, 8	5
Output Noise			2.5		µVRMS	TA = +25°C, DR =15 SPS, PGA = 1, VIN+ = VIN- = GND	5
Integral Non-Linearity	INL		10		ppm of FSR	DR = 15 SPS	5
Internal Reference Voltage	VREF		2.048		V		5
Gain Error			0.1		%	PGA = 1, DR = 15 SPS	5
PGA Gain Error Match			0.1		%	Between any 2 PGA settings	5
Gain Error Drift			15		ppm/°C	PGA=1, DR=15 SPS	5
Offset Error	VOS		30		µV	PGA = 1, DR = 15 SPS	6
Offset Drift vs. Temperature			50		nV/°C		6
Gain vs. VDD			5		ppm/V	TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1	6
Power Supply Rejection at DC Input			100		dB	TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1	6
Addr_Low	Addr_Low	0		0.2	V	VSS to 0.2VDD; device reads logic low (MCP3427/8 only)	6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	MS = Plastic Micro Small Outline (MSOP), 8-lead SN = Plastic Small Outline SOIC, 8-lead	53

CAD (KiCad official)

Symbol: MCP3426A1-E
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: mcp3426a1-e-etched.step / mcp3426a1-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp3426a1-e.step / mcp3426a1-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (56 pp, sha256 3d9cc322b8fd7415, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

MCP3426A1-E

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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