component
MCP3422A0T-E
Public Made by Adomby adom
Microchip Tech Analog To Digital Converters (ADCs), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MCP3422A0T-E
Microchip Tech · Analog To Digital Converters (ADCs) · SOIC-8
MCP3422A0T-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CH1+ | input | Positive differential analog input of channel 1; input range is VSS-0.3V to VDD+0.3V. |
| 2 | CH1- | input | Negative differential analog input of channel 1; may be tied to VSS for single-ended operation, range VSS-0.3V to VDD+0.3V. |
| 3 | VDD | power_in | Positive supply, 2.7V to 5.5V for specified operation, with about 0.1 µF ceramic bypass to ground and an optional additional 10 µF tantalum. |
| 4 | SDA | bidirectional | Open-drain N-channel serial data pin of the I2C interface that needs a pull-up resistor to VDD (5 kΩ to 10 kΩ for standard and fast modes, under 1 kΩ for high-speed mode). |
| 5 | SCL | input | Serial clock input of the I2C interface (slave only, open-drain N-channel) that needs a pull-up resistor to VDD (5 kΩ to 10 kΩ for standard and fast modes, under 1 kΩ for high-speed mode). |
| 6 | VSS | power_in | Ground pin and current return path, to be connected to a ground plane through a low impedance connection. |
| 7 | CH2+ | input | Positive differential analog input of channel 2; input range is VSS-0.3V to VDD+0.3V. |
| 8 | CH2- | input | Negative differential analog input of channel 2; may be tied to VSS for single-ended operation, range VSS-0.3V to VDD+0.3V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum Input Voltage Range | -0.3 | 0.3 | V | VSS-0.3 to VDD+0.3 (Note 1) | 5 | ||
| Data Rate 12 bits mode | DR | 176 | 240 | 328 | SPS | 12 bits mode | 5 |
| Data Rate 14 bits mode | DR | 44 | 60 | 82 | SPS | 14 bits mode | 5 |
| Data Rate 16 bits mode | DR | 11 | 15 | 20.5 | SPS | 16 bits mode | 5 |
| Data Rate 18 bits mode | DR | 2.75 | 3.75 | 5.1 | SPS | 18 bits mode | 5 |
| Integral Non-Linearity | INL | 10 | 35 | ppm of FSR | DR = 3.75 SPS, FSR = Full Scale Range (Note 5) | 5 | |
| Gain Error | 0.05 | 0.35 | % | PGA = 1, DR = 3.75 SPS | 5 | ||
| Offset Error | VOS | 15 | 55 | µV | Tested at PGA = 1, DR = 3.75 SPS | 6 | |
| Supply Voltage Range | VDD | 2.7 | 5.5 | V | 6 | ||
| Supply Current during Conversion | IDDA | 145 | 180 | µA | VDD = 5.0V | 6 | |
| Supply Current during Conversion | IDDA | 135 | µA | VDD = 3.0V | 6 | ||
| Supply Current during Standby Mode | IDDS | 0.3 | 1 | µA | VDD = 5.0V | 6 | |
| High level input voltage | VIH | 0.7 | V | at SDA and SCL pins; min is 0.7VDD, max VDD (min shown as 0.7 x VDD factor) | 6 | ||
| Low level input voltage | VIL | 0.3 | V | at SDA and SCL pins; max is 0.3VDD (factor shown) | 6 | ||
| Low level output voltage | VOL | 0.4 | V | IOL = 3 mA | 6 | ||
| Hysteresis of Schmidt Trigger for inputs | VHYST | 0.05 | V | fSCL = 100 kHz; min is 0.05VDD (factor shown) (Note 7) | 6 | ||
| Supply Current when I2C bus line is active | IDDB | 10 | µA | Device is in standby mode while I2C bus is active | 6 | ||
| Input Leakage Current high | IILH | 1 | µA | VIH = 5.5V | 6 | ||
| Input Leakage Current low | IILL | -1 | µA | VIL = GND | 6 | ||
| Pin capacitance | CPIN | 4 | 10 | pF | 6 | ||
| I2C Bus Capacitance | Cb | 400 | pF | 6 | |||
| Resolution and No Missing Codes | 12 | Bits | DR = 240 SPS | 5 | |||
| Resolution and No Missing Codes | 14 | Bits | DR = 60 SPS | 5 | |||
| Resolution and No Missing Codes | 16 | Bits | DR = 15 SPS | 5 | |||
| Resolution and No Missing Codes | 18 | Bits | DR = 3.75 SPS | 5 | |||
| Differential Input Impedance | ZIND | 2.25 | MΩ | During normal mode operation, 2.25/PGA (Note 2) | 5 | ||
| Common Mode input Impedance | ZINC | 25 | MΩ | PGA = 1, 2, 4, 8 | 5 | ||
| Output Noise | 1.5 | µVRMS | TA = +25°C, DR = 3.75 SPS, PGA = 1, VIN+ = VIN- = GND | 5 | |||
| PGA Gain Error Match | 0.1 | % | Between any 2 PGA settings | 6 | |||
| Gain Error Drift | 15 | ppm/°C | PGA=1, DR=3.75 SPS | 6 | |||
| Offset Drift vs. Temperature | 50 | nV/°C | 6 | ||||
| Common-Mode Rejection | 105 | dB | at DC and PGA =1 | 6 | |||
| Common-Mode Rejection | 110 | dB | at DC and PGA =8, TA = +25°C | 6 | |||
| Gain vs. VDD | 5 | ppm/V | TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1 | 6 | |||
| Power Supply Rejection at DC Input | 100 | dB | TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1 | 6 | |||
| Supply voltage | VDD | 7 | V | 5 | |||
| Current at Input Pins | -2 | 2 | mA | ±2 mA | 5 | ||
| Current at Output and Supply Pins | -10 | 10 | mA | ±10 mA | 5 | ||
| Storage Temperature | -65 | 150 | °C | 5 | |||
| Ambient Temp. with power applied | -55 | 125 | °C | 5 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 5 | |||
| Specified Temperature Range | TA | -40 | 85 | °C | 7 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | 7 | ||
| Thermal Resistance, 8L-SOIC | θJA | 149.5 | °C/W | 7 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | SL = Plastic SOIC (150 mil Body), 14-lead SN = Plastic SOIC (3.90mm Body), 8-lead, | 55 |
CAD (KiCad official)
- Symbol:
MCP3422A0T-E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp3422a0t-e-etched.step/mcp3422a0t-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp3422a0t-e.step/mcp3422a0t-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (58 pp, sha256
3850891a8c0460ab, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP3422A0T-E
**Microchip Tech** · Analog To Digital Converters (ADCs) · SOIC-8
MCP3422A0T-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CH1+ | input | Positive differential analog input of channel 1; input range is VSS-0.3V to VDD+0.3V. |
| 2 | CH1- | input | Negative differential analog input of channel 1; may be tied to VSS for single-ended operation, range VSS-0.3V to VDD+0.3V. |
| 3 | VDD | power_in | Positive supply, 2.7V to 5.5V for specified operation, with about 0.1 µF ceramic bypass to ground and an optional additional 10 µF tantalum. |
| 4 | SDA | bidirectional | Open-drain N-channel serial data pin of the I2C interface that needs a pull-up resistor to VDD (5 kΩ to 10 kΩ for standard and fast modes, under 1 kΩ for high-speed mode). |
| 5 | SCL | input | Serial clock input of the I2C interface (slave only, open-drain N-channel) that needs a pull-up resistor to VDD (5 kΩ to 10 kΩ for standard and fast modes, under 1 kΩ for high-speed mode). |
| 6 | VSS | power_in | Ground pin and current return path, to be connected to a ground plane through a low impedance connection. |
| 7 | CH2+ | input | Positive differential analog input of channel 2; input range is VSS-0.3V to VDD+0.3V. |
| 8 | CH2- | input | Negative differential analog input of channel 2; may be tied to VSS for single-ended operation, range VSS-0.3V to VDD+0.3V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum Input Voltage Range | | -0.3 | | 0.3 | V | VSS-0.3 to VDD+0.3 (Note 1) | 5 |
| Data Rate 12 bits mode | DR | 176 | 240 | 328 | SPS | 12 bits mode | 5 |
| Data Rate 14 bits mode | DR | 44 | 60 | 82 | SPS | 14 bits mode | 5 |
| Data Rate 16 bits mode | DR | 11 | 15 | 20.5 | SPS | 16 bits mode | 5 |
| Data Rate 18 bits mode | DR | 2.75 | 3.75 | 5.1 | SPS | 18 bits mode | 5 |
| Integral Non-Linearity | INL | | 10 | 35 | ppm of FSR | DR = 3.75 SPS, FSR = Full Scale Range (Note 5) | 5 |
| Gain Error | | | 0.05 | 0.35 | % | PGA = 1, DR = 3.75 SPS | 5 |
| Offset Error | VOS | | 15 | 55 | µV | Tested at PGA = 1, DR = 3.75 SPS | 6 |
| Supply Voltage Range | VDD | 2.7 | | 5.5 | V | | 6 |
| Supply Current during Conversion | IDDA | | 145 | 180 | µA | VDD = 5.0V | 6 |
| Supply Current during Conversion | IDDA | | 135 | | µA | VDD = 3.0V | 6 |
| Supply Current during Standby Mode | IDDS | | 0.3 | 1 | µA | VDD = 5.0V | 6 |
| High level input voltage | VIH | 0.7 | | | V | at SDA and SCL pins; min is 0.7VDD, max VDD (min shown as 0.7 x VDD factor) | 6 |
| Low level input voltage | VIL | | | 0.3 | V | at SDA and SCL pins; max is 0.3VDD (factor shown) | 6 |
| Low level output voltage | VOL | | | 0.4 | V | IOL = 3 mA | 6 |
| Hysteresis of Schmidt Trigger for inputs | VHYST | 0.05 | | | V | fSCL = 100 kHz; min is 0.05VDD (factor shown) (Note 7) | 6 |
| Supply Current when I2C bus line is active | IDDB | | | 10 | µA | Device is in standby mode while I2C bus is active | 6 |
| Input Leakage Current high | IILH | | | 1 | µA | VIH = 5.5V | 6 |
| Input Leakage Current low | IILL | -1 | | | µA | VIL = GND | 6 |
| Pin capacitance | CPIN | | 4 | 10 | pF | | 6 |
| I2C Bus Capacitance | Cb | | | 400 | pF | | 6 |
| Resolution and No Missing Codes | | 12 | | | Bits | DR = 240 SPS | 5 |
| Resolution and No Missing Codes | | 14 | | | Bits | DR = 60 SPS | 5 |
| Resolution and No Missing Codes | | 16 | | | Bits | DR = 15 SPS | 5 |
| Resolution and No Missing Codes | | 18 | | | Bits | DR = 3.75 SPS | 5 |
| Differential Input Impedance | ZIND | | 2.25 | | MΩ | During normal mode operation, 2.25/PGA (Note 2) | 5 |
| Common Mode input Impedance | ZINC | | 25 | | MΩ | PGA = 1, 2, 4, 8 | 5 |
| Output Noise | | | 1.5 | | µVRMS | TA = +25°C, DR = 3.75 SPS, PGA = 1, VIN+ = VIN- = GND | 5 |
| PGA Gain Error Match | | | 0.1 | | % | Between any 2 PGA settings | 6 |
| Gain Error Drift | | | 15 | | ppm/°C | PGA=1, DR=3.75 SPS | 6 |
| Offset Drift vs. Temperature | | | 50 | | nV/°C | | 6 |
| Common-Mode Rejection | | | 105 | | dB | at DC and PGA =1 | 6 |
| Common-Mode Rejection | | | 110 | | dB | at DC and PGA =8, TA = +25°C | 6 |
| Gain vs. VDD | | | 5 | | ppm/V | TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1 | 6 |
| Power Supply Rejection at DC Input | | | 100 | | dB | TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1 | 6 |
| Supply voltage | VDD | | | 7 | V | | 5 |
| Current at Input Pins | | -2 | | 2 | mA | ±2 mA | 5 |
| Current at Output and Supply Pins | | -10 | | 10 | mA | ±10 mA | 5 |
| Storage Temperature | | -65 | | 150 | °C | | 5 |
| Ambient Temp. with power applied | | -55 | | 125 | °C | | 5 |
| Maximum Junction Temperature | TJ | | | 150 | °C | | 5 |
| Specified Temperature Range | TA | -40 | | 85 | °C | | 7 |
| Operating Temperature Range | TA | -40 | | 125 | °C | | 7 |
| Thermal Resistance, 8L-SOIC | θJA | | 149.5 | | °C/W | | 7 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | SL = Plastic SOIC (150 mil Body), 14-lead SN = Plastic SOIC (3.90mm Body), 8-lead, | 55 |
## CAD (KiCad official)
- Symbol: `MCP3422A0T-E`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `mcp3422a0t-e-etched.step` / `mcp3422a0t-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp3422a0t-e.step` / `mcp3422a0t-e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/mcp3422a0t-e-datasheet.pdf) (58 pp, sha256 `3850891a8c0460ab`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp3422a0t-e-datasheet.pdf)