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MCP33151-05T-E

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Microchip Tech Analog To Digital Converters (ADC), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MCP33151-05T-E

Microchip Tech · Analog To Digital Converters (ADC) · MSOP-10

MCP33151-05T-E from Microchip Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREF power_in External single-ended reference voltage input, valid from AVDD to 5.1V, which sets the 0V to VREF input full-scale range; decouple with a 10 µF tantalum capacitor (10V rating).
2 AVDD power_in Analog supply voltage input, 1.8V, to be decoupled with a 1 µF ceramic capacitor placed close to the pin.
3 AIN+ input Analog input pin; in single-ended operation the input full-scale range is 0V to VREF, referenced to AIN-.
4 AIN- power_in Ground reference pin for the analog input, to be connected to the ground reference of the analog input signal.
5 GND power_in Power supply ground reference, common to both the analog supply (AVDD) and the digital I/O supply (DVIO).
6 CNVST input Conversion start control and active-low SPI chip select: a new conversion starts on the rising edge of CNVST, and output data is presented on SDO when CNVST is lowered.
7 SDO output SPI-compatible serial data output that shifts ADC conversion data out MSB first, clocked by SCLK.
8 SCLK input SPI-compatible serial data clock input that synchronously shifts out the ADC output; clock rate up to 100 MHz.
9 SDI input SPI-compatible serial data digital input that must be tied to DVIO for normal operation.
10 DVIO power_in Digital input/output interface supply voltage, 1.7V to 5.5V, to be decoupled with a 0.1 µF ceramic capacitor.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package MSOP-10
Category Data Acquisition
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External Analog Supply Voltage (AVDD) AVDD -0.3 2 V 3
External Digital Supply Voltage (DVIO) DVIO -0.3 5.8 V 3
External Reference Voltage (VREF) VREF -0.3 5.8 V 3
Analog Inputs w.r.t GND -0.3 V 3
Current at Input Pins -2 2 mA 3
Current at Output and Supply Pins -250 250 mA 3
Storage Temperature -65 150 °C 3
Maximum Junction Temperature (TJ) TJ 150 °C 3
ESD Protection on all Pins (HBM) 4 kV HBM 3
ESD Protection on all Pins (CDM) 2 kV CDM 3
Analog Supply Voltage Range AVDD 1.7 1.8 1.9 V Note 3 3
Digital Input/Output Interface Voltage Range DVIO 1.7 5.5 V Note 3 3
Analog Supply Current at AVDD Pin: During Conversion IDDAN 330 600 µA fs = 500 ksps (MCP331X1-05) 3
Reference Voltage VREF 5.1 V Note 2, Note 3 4
Reference Load Current at VREF Pin: During Conversion IREF 110 180 µA fs = 500 ksps (MCP331X1-05) 4
Input Voltage Range VIN+ -0.1 V Note 2 4
Input Full-Scale Voltage Range FSR 0 VPP Note 2 4
Leakage Current at Analog Input Pin ILEAK_AN_INPUT -200 2.2 200 nA During input acquisition (tACQ) 4
Resolution (No Missing Codes) 14 Bits MCP33151-10 and MCP33151-05 4
Sample Rate (Throughput Rate) fs 500 ksps MCP331X1-05 4
Integral Nonlinearity INL -1.5 0.39 1.5 LSB MCP33151-10 and MCP33151-05 5
Differential Nonlinearity DNL -0.8 0.11 0.8 LSB MCP33151-10 and MCP33151-05 5
Offset Error -1.62 0.4 1.62 mV MCP33151-10 and MCP33151-05 5
Signal-to-Noise Ratio SNR 78.7 80.4 dBFS VREF = 5V, fIN = 10 kHz 5
Self-Calibration Time tCAL 500 650 ms Note 2 6
Low-Level Input Voltage VIL -0.3 V DVIO ≥ 2.3V 7
Input Leakage Current ILI -1 1 µA CNVST/SDI/SCLK = GND or DVIO 7
Output Leakage Current ILO -1 1 µA Output is high-Z, SDO = GND or DVIO 7
Serial Clock Frequency fSCLK 100 MHz See tSCLK specification 8
SCLK Period tSCLK 10 ns DVIO ≥ 3.3V, fSCLK = 100 MHz (Max.) 8
SCLK Period tSCLK 12 ns DVIO ≥ 2.3V, fSCLK = 83.3 MHz (Max.) 8
SCLK Period tSCLK 16 ns DVIO ≥ 1.7V, fSCLK = 62.5 MHz (Max.) 8
SCLK Low Time tSCLK_L 3 ns DVIO ≥ 2.3V 8
SCLK Low Time tSCLK_L 4.5 ns DVIO ≥ 1.7V 8
SCLK High Time tSCLK_H 3 ns DVIO ≥ 2.3V 8
SCLK High Time tSCLK_H 4.5 ns DVIO ≥ 1.7V 8
Output Valid from SCLK Low tDO 10 ns DVIO ≥ 3.3V 8
Output Valid from SCLK Low tDO 12 ns DVIO ≥ 2.3V 8
Output Valid from SCLK Low tDO 16 ns DVIO ≥ 1.7V 8
Quiet Time tQUIET 10 ns Note 2 8
SDI Valid Setup Time tSU_SDIH_CNV 5 ns SDI High to CNVST Rising Edge 8
CNVST Pulse Width High Time tCNVH 10 ns 8
Output Enable Time tEN 10 ns DVIO ≥ 2.3V 8
Output Enable Time tEN 15 ns DVIO ≥ 1.7V 8
Output Disable Time tDIS 15 ns Note 2 8
Input Acquisition Time tACQ 600 800 ns 8
Data Conversion Time tCNV 1200 1400 ns 8
Time Between Conversions tCYC 2 µs tCYC =tACQ +tCNV, fS = 500 ksps 8
Operating Temperature Range TA -40 125 °C Note 1 9
Storage Temperature Range TA -65 150 °C Note 1 9
Thermal Resistance, MSOP-10 JA 202 °C/W 9

CAD (KiCad official)

  • Symbol: MCP33151-05T-E
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: mcp33151-05t-e-etched.step / mcp33151-05t-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp33151-05t-e.step / mcp33151-05t-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (55 pp, sha256 e4cf1ff6180a22bc, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF