component
MCP33131D-10-E
Public Made by Adomby adom
Microchip Tech Analog To Digital Converters (ADCs), TDFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMCP33131D-10-E
Microchip Tech · Analog To Digital Converters (ADCs) · TDFN-10-EP(3x3)
MCP33131D-10-E from Microchip Tech, in a TDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Reference voltage input (2.5V - 5.1V) that sets the input full-scale range from 0V to VREF, to be decoupled with a 10 µF tantalum capacitor. |
| 2 | AVDD | power_in | DC supply voltage input for the analog section, 1.8V, to be decoupled with a 1 µF ceramic capacitor. |
| 3 | AIN+ | input | Differential positive analog input, with absolute maximum limits of VREF + 0.1V and GND - 0.1V. |
| 4 | AIN- | input | Differential negative analog input, with absolute maximum limits of VREF + 0.1V and GND - 0.1V. |
| 5 | GND | power_in | Power supply ground reference, a common ground for both the analog supply (AVDD) and the digital I/O supply (DVIO). |
| 6 | CNVST | input | Active-low SPI chip-select digital input that starts a new conversion on its rising edge; output data is available on SDO when the host lowers CNVST. |
| 7 | SDO | output | SPI-compatible serial digital data output that shifts ADC conversion data out MSB first on the SCLK clock. |
| 8 | SCLK | input | SPI-compatible serial data clock digital input (up to 100 MHz) that synchronously shifts the ADC output out. |
| 9 | SDI | input | SPI-compatible serial data digital input that must be tied to DVIO for normal operation. |
| 10 | DVIO | power_in | DC supply voltage for the digital input/output interface (1.7V - 5.5V), to be decoupled with a 0.1 µF ceramic capacitor. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TDFN-10-EP(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External Analog Supply Voltage | AVDD | -0.3 | 2 | V | 3 | ||
| External Digital Supply Voltage | DVIO | -0.3 | 5.8 | V | 3 | ||
| External Reference Voltage | VREF | -0.3 | 5.8 | V | 3 | ||
| Current at Input Pins | -2 | 2 | mA | 3 | |||
| Current at Output and Supply Pins | -250 | 250 | mA | 3 | |||
| Storage Temperature | -65 | 150 | °C | 3 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 3 | |||
| Analog Supply Voltage Range | AVDD | 1.7 | 1.8 | 1.9 | V | (Note 3) | 3 |
| Digital Input/Output Interface Voltage Range | DVIO | 1.7 | 5.5 | V | (Note 3) | 3 | |
| Analog Supply Current at AVDD pin: During Conversion | IDDAN | 1.6 | 2.4 | mA | fs = 1 Msps (MCP331x1D-10) | 3 | |
| Analog Supply Current at AVDD pin: During Standby | IDDAN_STBY | 0.8 | µA | During input acquisition (tACQ) | 3 | ||
| Digital Supply Current At DVDD pin: During Output Data Reading | IIO_DATA | 290 | A | fs = 1 Msps (MCP331x1D-10) | 3 | ||
| Digital Supply Current At DVDD pin: During Standby | IIO_STBY | 30 | nA | During input acquisition (tACQ) | 3 | ||
| Reference Voltage | VREF | 2.5 | 5.1 | V | -40°C ≤ TA ≤ 85°C | 3 | |
| Reference Voltage | VREF | 2.7 | 5.1 | V | 85°C < TA ≤ 125°C | 3 | |
| Operating Temperature Range | TA | -40 | 125 | °C | (Note 1) | 8 | |
| Input Voltage Range VIN+ | VIN+ | -0.1 | V | Differential Input: VIN = (VIN+ - VIN-); upper limit VREF+0.1 V | 4 | ||
| Input Voltage Range VIN- | VIN- | -0.1 | V | Differential Input: VIN = (VIN+ - VIN-); upper limit VREF+0.1 V | 4 | ||
| Input Sampling Capacitance | CS | 31 | pF | (Note 1) | 4 | ||
| -3dB Input Bandwidth | BW-3dB | 25 | MHz | (Note 1) | 4 | ||
| Aperture Delay | 2.5 | ns | Time delay between CNVST rising edge and when input is sampled | 4 | |||
| Leakage Current at Analog Input Pin | ILEAK_AN_INPUT | -200 | 2 | 200 | nA | During input acquisition (tACQ) | 4 |
| Sample Rate (Throughput rate) | fs | 1 | Msps | MCP331x1D-10 | 4 | ||
| Resolution (No Missing Codes) | 16 | Bits | MCP33131D-10 and MCP33131D-05 | 4 | |||
| Integral Nonlinearity | INL | -6 | 2 | 6 | LSB | MCP33131D-10 and MCP33131D-05 | 4 |
| Differential Nonlinearity | DNL | -0.98 | 0.8 | 1.8 | LSB | MCP33131D-10 and MCP33131D-05 | 4 |
| Offset Error | -2.3 | 0.1 | 2.3 | mV | MCP33131D-10 and MCP33131D-05 | 4 | |
| Offset Error Drift with Temperature | 0.8 | V/oC | 4 | ||||
| Gain Error | GER | 2 | LSB | MCP33131D-10 and MCP33131D-05 | 4 | ||
| Gain Error Drift with temperature | 0.35 | V/oC | 4 | ||||
| Input common-mode rejection ratio | CMRR | 84 | dB | 4 | |||
| Power Supply Rejection Ratio | PSRR | 70 | dB | (Note 5) | 4 | ||
| Signal-to-Noise Ratio MCP33131D-10 and MCP33131D-05: 16-bit ADC | SNR | 88.7 | 91.3 | dBFS | VREF = 5V, fIN = 10 kHz | 5 | |
| Signal-to-Noise and Distortion Ratio MCP33131D-10 and MCP33131D-05: 16-bit ADC | SINAD | 91 | dBFS | VREF = 5V, fIN = 10 kHz | 5 | ||
| Spurious Free Dynamic Range MCP33131D-10 and MCP33131D-05: 16-bit ADC | SFDR | 103.5 | dBc | VREF = 5V, fIN = 10 kHz | 6 | ||
| Total Harmonic Distortion MCP33131D-10 and MCP33131D-05: 16-bit ADC | THD | -99.3 | dBc | VREF = 5V, fIN = 10 kHz | 6 | ||
| Self-Calibration Time | tCAL | 500 | 650 | ms | (Note 2) | 7 | |
| Input leakage current | ILI | -1 | 1 | µA | CNVST/SDI/SCLK = GND or DVIO | 7 | |
| Serial Clock frequency | fSCLK | 100 | MHz | See tSCLK specification | 8 | ||
| SCLK Period | tSCLK | 10 | ns | DVIO ≥ 3.3V, fSCLK = 100 MHz (Max) | 8 | ||
| SCLK Period | tSCLK | 12 | ns | DVIO ≥ 2.3V, fSCLK = 83.3 MHz (Max) | 8 | ||
| SCLK Period | tSCLK | 16 | ns | DVIO ≥ 1.7V, fSCLK = 62.5 MHz (Max) | 8 | ||
| SCLK Low Time | tSCLK_L | 3 | ns | DVIO ≥ 2.3V | 8 | ||
| SCLK High Time | tSCLK_H | 3 | ns | DVIO ≥ 2.3V | 8 | ||
| Output Valid from SCLK Low | tDO | 9.5 | ns | DVIO ≥ 3.3V | 8 | ||
| Output Valid from SCLK Low | tDO | 12 | ns | DVIO ≥ 2.3V | 8 | ||
| Output Valid from SCLK Low | tDO | 16 | ns | DVIO ≥ 1.7V | 8 | ||
| Quiet time | tQUIET | 10 | ns | (Note 2) | 8 | ||
| SDI Valid Setup time | tSU_SDIH_CNV | 5 | ns | SDI High to CNVST Rising Edge | 8 | ||
| CNVST Pulse Width High Time | tCNVH | 10 | ns | 8 | |||
| Output Enable Time | tEN | 10 | ns | DVIO ≥ 2.3V | 8 | ||
| Output Enable Time | tEN | 15 | ns | DVIO ≥ 1.7V | 8 | ||
| Output Disable Time | tDIS | 15 | ns | (Note 2) | 8 | ||
| Input Acquisition Time MCP331x1D-10 | tACQ | 290 | ns | -40°C ≤ TA ≤ 85°C | 8 | ||
| Input Acquisition Time MCP331x1D-10 | tACQ | 250 | ns | 85°C < TA ≤ 125°C | 8 | ||
| Time between Conversions MCP331x1D-10 | tCYC | 1 | µs | tCYC = tACQ + tCNV, fS = 1 Msps | 8 | ||
| Thermal Resistance, TDFN-10 | JA | 68 | °C/W | 8 |
CAD (KiCad official)
- Symbol:
MCP33131D-10-E - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: TDFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
mcp33131d-10-e-etched.step/mcp33131d-10-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp33131d-10-e.step/mcp33131d-10-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (59 pp, sha256
a78a66eb6299039c, retrieved 2026-10-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).