component
MCP33131-05-E
Public Made by Adomby adom
Microchip Tech Analog To Digital Converters (ADCs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MCP33131-05-E
Microchip Tech · Analog To Digital Converters (ADCs) · MSOP-10
MCP33131-05-E from Microchip Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | External reference voltage input that must be 2.5V to 5.1V and sets the input full-scale range from 0V to VREF; decouple with a 10 µF tantalum capacitor. |
| 2 | AVDD | power_in | Analog supply voltage input rated at 1.8V, to be decoupled with a 1 µF ceramic capacitor. |
| 3 | AIN+ | input | Analog input carrying the signal to convert, with the input full-scale range of 0V to VREF. |
| 4 | AIN- | passive | Ground reference pin for the analog input that must be connected to the ground reference of the analog input signal. |
| 5 | GND | power_in | Common ground reference for both the analog supply (AVDD) and the digital I/O supply (DVIO). |
| 6 | CNVST | input | Active-low SPI chip-select digital input that starts a new conversion on its rising edge; lowering it after conversion presents output data on SDO. |
| 7 | SDO | output | SPI-compatible serial data output that shifts conversion data out MSB first, clocked by SCLK. |
| 8 | SCLK | input | SPI-compatible serial data clock input that synchronously shifts the ADC output out on SDO. |
| 9 | SDI | input | SPI-compatible serial data digital input that must be tied to DVIO for normal operation. |
| 10 | DVIO | power_in | Digital input/output interface supply rated 1.7V to 5.5V, to be decoupled with a 0.1 µF ceramic capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | MSOP-10 |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External Analog Supply Voltage (AVDD) absolute maximum | AVDD | -0.3 | 2 | V | 3 | ||
| External Digital Supply Voltage (DVIO) absolute maximum | DVIO | -0.3 | 5.8 | V | 3 | ||
| External Reference Voltage (VREF) absolute maximum | VREF | -0.3 | 5.8 | V | 3 | ||
| Analog Inputs w.r.t GND (absolute maximum; upper limit printed as VREF+0.3V) | -0.3 | V | 3 | ||||
| Current at Input Pins | -2 | 2 | mA | 3 | |||
| Current at Output and Supply Pins | -250 | 250 | mA | 3 | |||
| Maximum Junction Temperature (TJ) | TJ | 150 | °C | 3 | |||
| ESD protection | 2 | kV | HBM | 3 | |||
| ESD protection | 200 | V | MM | 3 | |||
| Analog Supply Voltage Range | AVDD | 1.7 | 1.8 | 1.9 | V | 3 | |
| Digital Input/Output Interface Voltage Range | DVIO | 1.7 | 5.5 | V | 3 | ||
| External Reference Voltage Input (Reference Voltage) | VREF | 2.5 | 5.1 | V | -40°C ≤ TA ≤ 85°C | 3 | |
| External Reference Voltage Input (Reference Voltage) | VREF | 2.7 | 5.1 | V | 85°C < TA ≤ 125°C | 3 | |
| Analog Supply Current at AVDD pin: During Conversion | IDDAN | 1.4 | 2 | mA | fs = 500 kSPS (MCP331x1-05) | 3 | |
| Reference Load Current at VREF pin: During Conversion | IREF | 220 | 360 | µA | fs = 500 kSPS (MCP331x1-05) | 3 | |
| Input Voltage Range (VIN+) | VIN+ | -0.1 | V | 4 | |||
| Input Full-Scale Voltage Range | FSR | 0 | VPP | 4 | |||
| Leakage Current at Analog Input Pin | ILEAK_AN_INPUT | -200 | 2 | 200 | nA | During input acquisition (tACQ) | 4 |
| Sample Rate (Throughput rate) | fs | 500 | kSPS | MCP331x1-05 | 4 | ||
| Resolution (No Missing Codes) | 16 | Bits | MCP33131-10 and MCP33131-05 | 4 | |||
| Integral Nonlinearity | INL | -6 | 2.2 | 6 | LSB | MCP33131-10 and MCP33131-05 | 4 |
| Differential Nonlinearity | DNL | -0.98 | 0.9 | 1.8 | LSB | MCP33131-10 and MCP33131-05 | 4 |
| Offset Error | -2.3 | 0.1 | 2.3 | mV | MCP33131-10 and MCP33131-05 | 4 | |
| Signal-to-Noise Ratio (SNR) | SNR | 83.5 | 86.7 | dBFS | VREF = 5V, fIN = 10 kHz | 5 | |
| High-level input voltage / Low-level input voltage (VIL, DVIO ≥ 2.3V; max printed as 0.3*DVIO) | VIL | -0.3 | V | DVIO ≥ 2.3V | 7 | ||
| Low-level input voltage (VIL, DVIO < 2.3V; max printed as 0.2*DVIO) | VIL | -0.3 | V | DVIO < 2.3V | 7 | ||
| Input leakage current | ILI | -1 | 1 | µA | CNVST/SDI/SCLK = GND or DVIO | 7 | |
| Output leakage current | ILO | -1 | 1 | µA | Output is high-Z, SDO = GND or DVIO | 7 | |
| Self-Calibration Time | tCAL | 500 | 650 | ms | 7 | ||
| Serial Clock frequency | fSCLK | 100 | MHz | See tSCLK specification | 8 | ||
| SCLK Period | tSCLK | 10 | ns | DVIO ≥ 3.3V, fSCLK = 100 MHz (Max) | 8 | ||
| SCLK Period | tSCLK | 12 | ns | DVIO ≥ 2.3V, fSCLK = 83.3 MHz (Max) | 8 | ||
| SCLK Period | tSCLK | 16 | ns | DVIO ≥ 1.7V, fSCLK = 62.5 MHz (Max) | 8 | ||
| SCLK Low Time | tSCLK_L | 3 | ns | DVIO ≥ 2.3V | 8 | ||
| SCLK Low Time | tSCLK_L | 4.5 | ns | DVIO ≥ 1.7V | 8 | ||
| SCLK High Time | tSCLK_H | 3 | ns | DVIO ≥ 2.3V | 8 | ||
| SCLK High Time | tSCLK_H | 4.5 | ns | DVIO ≥ 1.7V | 8 | ||
| Output Valid from SCLK Low | tDO | 9.5 | ns | DVIO ≥ 3.3V | 8 | ||
| Output Valid from SCLK Low | tDO | 12 | ns | DVIO ≥ 2.3V | 8 | ||
| Output Valid from SCLK Low | tDO | 16 | ns | DVIO ≥ 1.7V | 8 | ||
| Quiet time | tQUIET | 10 | ns | 8 | |||
| SDI Valid Setup time | tSU_SDIH_CNV | 5 | ns | SDI High to CNVST Rising Edge | 8 | ||
| CNVST Pulse Width High Time | tCNVH | 10 | ns | 8 | |||
| Output Enable Time | tEN | 10 | ns | DVIO ≥ 2.3V | 8 | ||
| Output Enable Time | tEN | 15 | ns | DVIO ≥ 1.7V | 8 | ||
| Output Disable Time | tDIS | 15 | ns | 8 | |||
| Input Acquisition Time (MCP331x1-05) | tACQ | 700 | 800 | ns | -40°C ≤ TA ≤ 125°C | 8 | |
| Data Conversion Time (MCP331x1-05) | tCNV | 1200 | 1300 | ns | -40°C ≤ TA ≤ 125°C | 8 | |
| Time between Conversions (MCP331x1-05) | tCYC | 2 | µs | tCYC = tACQ + tCNV, fS = 500 kSPS | 8 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | 8 | ||
| Thermal Resistance, MSOP-10 | JA | 202 | °C/W | 8 |
CAD (KiCad official)
- Symbol:
MCP33131-05-E - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
mcp33131-05-e-etched.step/mcp33131-05-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp33131-05-e.step/mcp33131-05-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (54 pp, sha256
08adc037e7394a4c, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP33131-05-E
**Microchip Tech** · Analog To Digital Converters (ADCs) · MSOP-10
MCP33131-05-E from Microchip Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | External reference voltage input that must be 2.5V to 5.1V and sets the input full-scale range from 0V to VREF; decouple with a 10 µF tantalum capacitor. |
| 2 | AVDD | power_in | Analog supply voltage input rated at 1.8V, to be decoupled with a 1 µF ceramic capacitor. |
| 3 | AIN+ | input | Analog input carrying the signal to convert, with the input full-scale range of 0V to VREF. |
| 4 | AIN- | passive | Ground reference pin for the analog input that must be connected to the ground reference of the analog input signal. |
| 5 | GND | power_in | Common ground reference for both the analog supply (AVDD) and the digital I/O supply (DVIO). |
| 6 | CNVST | input | Active-low SPI chip-select digital input that starts a new conversion on its rising edge; lowering it after conversion presents output data on SDO. |
| 7 | SDO | output | SPI-compatible serial data output that shifts conversion data out MSB first, clocked by SCLK. |
| 8 | SCLK | input | SPI-compatible serial data clock input that synchronously shifts the ADC output out on SDO. |
| 9 | SDI | input | SPI-compatible serial data digital input that must be tied to DVIO for normal operation. |
| 10 | DVIO | power_in | Digital input/output interface supply rated 1.7V to 5.5V, to be decoupled with a 0.1 µF ceramic capacitor. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | MSOP-10 |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External Analog Supply Voltage (AVDD) absolute maximum | AVDD | -0.3 | | 2 | V | | 3 |
| External Digital Supply Voltage (DVIO) absolute maximum | DVIO | -0.3 | | 5.8 | V | | 3 |
| External Reference Voltage (VREF) absolute maximum | VREF | -0.3 | | 5.8 | V | | 3 |
| Analog Inputs w.r.t GND (absolute maximum; upper limit printed as VREF+0.3V) | | -0.3 | | | V | | 3 |
| Current at Input Pins | | -2 | | 2 | mA | | 3 |
| Current at Output and Supply Pins | | -250 | | 250 | mA | | 3 |
| Maximum Junction Temperature (TJ) | TJ | | | 150 | °C | | 3 |
| ESD protection | | | | 2 | kV | HBM | 3 |
| ESD protection | | | | 200 | V | MM | 3 |
| Analog Supply Voltage Range | AVDD | 1.7 | 1.8 | 1.9 | V | | 3 |
| Digital Input/Output Interface Voltage Range | DVIO | 1.7 | | 5.5 | V | | 3 |
| External Reference Voltage Input (Reference Voltage) | VREF | 2.5 | | 5.1 | V | -40°C ≤ TA ≤ 85°C | 3 |
| External Reference Voltage Input (Reference Voltage) | VREF | 2.7 | | 5.1 | V | 85°C < TA ≤ 125°C | 3 |
| Analog Supply Current at AVDD pin: During Conversion | IDDAN | | 1.4 | 2 | mA | fs = 500 kSPS (MCP331x1-05) | 3 |
| Reference Load Current at VREF pin: During Conversion | IREF | | 220 | 360 | µA | fs = 500 kSPS (MCP331x1-05) | 3 |
| Input Voltage Range (VIN+) | VIN+ | -0.1 | | | V | | 4 |
| Input Full-Scale Voltage Range | FSR | 0 | | | VPP | | 4 |
| Leakage Current at Analog Input Pin | ILEAK_AN_INPUT | -200 | 2 | 200 | nA | During input acquisition (tACQ) | 4 |
| Sample Rate (Throughput rate) | fs | | | 500 | kSPS | MCP331x1-05 | 4 |
| Resolution (No Missing Codes) | | 16 | | | Bits | MCP33131-10 and MCP33131-05 | 4 |
| Integral Nonlinearity | INL | -6 | 2.2 | 6 | LSB | MCP33131-10 and MCP33131-05 | 4 |
| Differential Nonlinearity | DNL | -0.98 | 0.9 | 1.8 | LSB | MCP33131-10 and MCP33131-05 | 4 |
| Offset Error | | -2.3 | 0.1 | 2.3 | mV | MCP33131-10 and MCP33131-05 | 4 |
| Signal-to-Noise Ratio (SNR) | SNR | 83.5 | 86.7 | | dBFS | VREF = 5V, fIN = 10 kHz | 5 |
| High-level input voltage / Low-level input voltage (VIL, DVIO ≥ 2.3V; max printed as 0.3*DVIO) | VIL | -0.3 | | | V | DVIO ≥ 2.3V | 7 |
| Low-level input voltage (VIL, DVIO < 2.3V; max printed as 0.2*DVIO) | VIL | -0.3 | | | V | DVIO < 2.3V | 7 |
| Input leakage current | ILI | -1 | | 1 | µA | CNVST/SDI/SCLK = GND or DVIO | 7 |
| Output leakage current | ILO | -1 | | 1 | µA | Output is high-Z, SDO = GND or DVIO | 7 |
| Self-Calibration Time | tCAL | | 500 | 650 | ms | | 7 |
| Serial Clock frequency | fSCLK | | | 100 | MHz | See tSCLK specification | 8 |
| SCLK Period | tSCLK | 10 | | | ns | DVIO ≥ 3.3V, fSCLK = 100 MHz (Max) | 8 |
| SCLK Period | tSCLK | 12 | | | ns | DVIO ≥ 2.3V, fSCLK = 83.3 MHz (Max) | 8 |
| SCLK Period | tSCLK | 16 | | | ns | DVIO ≥ 1.7V, fSCLK = 62.5 MHz (Max) | 8 |
| SCLK Low Time | tSCLK_L | 3 | | | ns | DVIO ≥ 2.3V | 8 |
| SCLK Low Time | tSCLK_L | 4.5 | | | ns | DVIO ≥ 1.7V | 8 |
| SCLK High Time | tSCLK_H | 3 | | | ns | DVIO ≥ 2.3V | 8 |
| SCLK High Time | tSCLK_H | 4.5 | | | ns | DVIO ≥ 1.7V | 8 |
| Output Valid from SCLK Low | tDO | | | 9.5 | ns | DVIO ≥ 3.3V | 8 |
| Output Valid from SCLK Low | tDO | | | 12 | ns | DVIO ≥ 2.3V | 8 |
| Output Valid from SCLK Low | tDO | | | 16 | ns | DVIO ≥ 1.7V | 8 |
| Quiet time | tQUIET | 10 | | | ns | | 8 |
| SDI Valid Setup time | tSU_SDIH_CNV | 5 | | | ns | SDI High to CNVST Rising Edge | 8 |
| CNVST Pulse Width High Time | tCNVH | 10 | | | ns | | 8 |
| Output Enable Time | tEN | | | 10 | ns | DVIO ≥ 2.3V | 8 |
| Output Enable Time | tEN | | | 15 | ns | DVIO ≥ 1.7V | 8 |
| Output Disable Time | tDIS | | | 15 | ns | | 8 |
| Input Acquisition Time (MCP331x1-05) | tACQ | 700 | 800 | | ns | -40°C ≤ TA ≤ 125°C | 8 |
| Data Conversion Time (MCP331x1-05) | tCNV | | 1200 | 1300 | ns | -40°C ≤ TA ≤ 125°C | 8 |
| Time between Conversions (MCP331x1-05) | tCYC | 2 | | | µs | tCYC = tACQ + tCNV, fS = 500 kSPS | 8 |
| Operating Temperature Range | TA | -40 | | 125 | °C | | 8 |
| Thermal Resistance, MSOP-10 | JA | | 202 | | °C/W | | 8 |
## CAD (KiCad official)
- Symbol: `MCP33131-05-E`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files: `mcp33131-05-e-etched.step` / `mcp33131-05-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp33131-05-e.step` / `mcp33131-05-e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://ww1.microchip.com/downloads/en/DeviceDoc/MCP33131-MCP33121-MCP33111-Family-Data-Sheet-DS20006122A.pdf) (54 pp, sha256 `08adc037e7394a4c`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp33131-05-e-datasheet.pdf)