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MCP33111D-05-E

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Microchip Tech Analog To Digital Converters (ADCs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

markdown

MCP33111D-05-E

Microchip Tech · Analog To Digital Converters (ADCs) · MSOP-10

MCP33111D-05-E from Microchip Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREF power_in Reference voltage input that must be supplied within 2.5V to 5.1V and should be decoupled with a 10 µF tantalum capacitor.
2 AVDD power_in Analog supply input that requires 1.8V and should be decoupled with a 1 µF ceramic capacitor.
3 AIN+ input Differential positive analog input whose absolute maximum range is GND - 0.1V to VREF + 0.1V.
4 AIN- input Differential negative analog input whose absolute maximum range is GND - 0.1V to VREF + 0.1V.
5 GND power_in Common ground reference for both the analog supply (AVDD) and the digital I/O supply (DVIO).
6 CNVST input Active-low SPI chip-select and conversion-start digital input, where a new conversion starts on its rising edge.
7 SDO output SPI-compatible serial data output that shifts conversion data out MSB first on SCLK.
8 SCLK input SPI-compatible serial data clock input that synchronously shifts out the ADC output, rated up to 100 MHz.
9 SDI input SPI-compatible serial data input that must be tied to DVIO for normal operation.
10 DVIO power_in Digital input/output interface supply that operates from 1.7V to 5.5V and should be decoupled with a 0.1 µF ceramic capacitor.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package MSOP-10
Category ADC/DAC/Data Conversion
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog Supply Voltage Range AVDD 1.7 1.8 1.9 V (Note 3) 3
Digital Input/Output Interface Voltage Range DVIO 1.7 5.5 V (Note 3) 3
Analog Supply Current During Conversion IDDAN 1.4 2 mA fs = 500 kSPS (MCP331x1D-05) 3
External Reference Voltage VREF 2.5 5.1 V -40°C ≤ TA ≤ 85°C 3
External Reference Voltage VREF 2.7 5.1 V 85°C < TA ≤ 125°C 3
Leakage Current at Analog Input Pin ILEAK_AN_INPUT -200 200 nA During input acquisition (tACQ) 4
Integral Nonlinearity INL -0.12 0.12 LSB MCP33111D-10 and MCP33111D-05 4
Differential Nonlinearity DNL -0.3 0.3 LSB MCP33111D-10 and MCP33111D-05 4
Offset Error -3.66 3.66 mV MCP33111D-10 and MCP33111D-05 4
Signal-to-Noise Ratio SNR 71.1 73.9 dBFS VREF = 5V, fIN = 10 kHz, MCP33111D-10 and MCP33111D-05 5
Sample Rate (Throughput rate) fs 500 kSPS MCP331x1D-05 throughput rate 8
Data Conversion Time tCNV 1200 1300 ns -40°C ≤ TA ≤ 125°C 8
Input Acquisition Time tACQ 700 800 ns -40°C ≤ TA ≤ 125°C 8
Time between Conversions tCYC 2 µs tCYC = tACQ + tCNV, fS = 500 kSPS 8
SCLK Period tSCLK 10 ns DVIO ≥ 3.3V, fSCLK = 100 MHz (Max) 8
SCLK Period tSCLK 12 ns DVIO ≥ 2.3V, fSCLK = 83.3 MHz (Max) 8
SCLK Period tSCLK 16 ns DVIO ≥ 1.7V, fSCLK = 62.5 MHz (Max) 8
SCLK Low Time tSCLK_L 3 ns DVIO ≥ 2.3V 8
SCLK Low Time tSCLK_L 4.5 ns DVIO ≥ 1.7V 8
SCLK High Time tSCLK_H 3 ns DVIO ≥ 2.3V 8
SCLK High Time tSCLK_H 4.5 ns DVIO ≥ 1.7V 8
Output Valid from SCLK Low tDO 9.5 ns DVIO ≥ 3.3V 8
Output Valid from SCLK Low tDO 12 ns DVIO ≥ 2.3V 8
Output Valid from SCLK Low tDO 16 ns DVIO ≥ 1.7V 8
Output Enable Time tEN 10 ns DVIO ≥ 2.3V 8
Output Enable Time tEN 15 ns DVIO ≥ 1.7V 8
Output Disable Time tDIS 15 ns (Note 2) 8
Quiet time tQUIET 10 ns (Note 2) 8
SDI Valid Setup time tSU_SDIH_CNV 5 ns SDI High to CNVST Rising Edge 8
CNVST Pulse Width High Time tCNVH 10 ns 8
Serial Clock frequency fSCLK 100 MHz See tSCLK specification 8
Self-Calibration Time tCAL 500 650 ms (Note 2) 7
Input leakage current ILI -1 1 µA CNVST/SDI/SCLK = GND or DVIO 7
Output leakage current ILO -1 1 µA Output is high-Z, SDO = GND or DVIO 7
Operating Temperature Range TA -40 125 °C (Note 1) 8
Storage Temperature Range TA -65 150 °C (Note 1) 8
External Analog Supply Voltage AVDD -0.3 2 V 3
External Digital Supply Voltage DVIO -0.3 5.8 V 3
External Reference Voltage VREF -0.3 5.8 V 3
Current at Input Pins -2 2 mA 3
Current at Output and Supply Pins -250 250 mA 3
Maximum Junction Temperature TJ 150 °C 3
ESD protection HBM 2 kV ESD protection on all pins, HBM 3
ESD protection MM 200 V ESD protection on all pins, MM 3
ESD protection CDM 2 kV ESD protection on all pins, CDM 3
Thermal Resistance, MSOP-10 JA 202 °C/W MSOP-10 package 8

CAD (KiCad official)

  • Symbol: MCP33111D-05-E
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: mcp33111d-05-e-etched.step / mcp33111d-05-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp33111d-05-e.step / mcp33111d-05-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (59 pp, sha256 a78a66eb6299039c, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF