# MCP3221A7T-E

**Microchip Tech** · Analog To Digital Converters (ADCs) · SOT-23-5

MCP3221A7T-E from Microchip Tech, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Supplies power to the device from +2.7V to 5.5V and provides the voltage reference for the conversion process. |
| 2 | VSS | power_in | Ground reference for the device, with VDD measured relative to this pin. |
| 3 | AIN | input | Single-ended analog input to the sample and hold circuitry, where the voltage for proper conversions can vary from VSS to VDD. |
| 4 | SDA | bidirectional | Open-drain serial data pin that transfers addresses and data and requires a pull-up resistor to VDD (typically 10 kΩ for 100 kHz and 2 kΩ for 400 kHz SCL). |
| 5 | SCL | input | Open-drain serial clock input that synchronizes data transfer on SDA and requires a pull-up resistor to VDD (typically 10 kΩ for 100 kHz and 2 kΩ for 400 kHz). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOT-23-5 |
| Category | ADC/DAC/Data Conversion |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Integral Nonlinearity | INL | -2 | 0.75 | 2 | LSB |  | 3 |
| Differential Nonlinearity | DNL | -1 | 0.5 | 1 | LSB | No missing codes | 3 |
| Offset Error |  | -2 | 0.75 | 2 | LSB |  | 3 |
| Gain Error |  | -3 | -1 | 3 | LSB |  | 3 |
| Analog Input Leakage Current |  | -1 |  | 1 | µA |  | 3 |
| Low-Level Output Voltage | VOL |  |  | 0.4 | V | IOL = 3 mA, RPU = 1.53 k | 3 |
| Input Leakage Current | ILI | -1 |  | 1 | µA | VIN = 0.1 VDD and 0.9 VDD | 3 |
| Output Leakage Current | ILO | -1 |  | 1 | µA | VOUT = 0.1 VSS and 0.9 VDD | 3 |
| Pin Capacitance | CIN, COUT |  |  | 10 | pF | TA = 25°C, f = 1 MHz; (Note 2) | 4 |
| Bus Capacitance | CB |  |  | 400 | pF | SDA drive low, 0.4V | 4 |
| Operating Voltage | VDD | 2.7 |  | 5.5 | V |  | 4 |
| Conversion Current | IDD |  | 175 | 250 | µA |  | 4 |
| Standby Current | IDDS |  | 0.005 | 1 | µA | SDA, SCL = VDD | 4 |
| Active Bus Current | IDDA |  |  | 120 | µA | Note 4 | 4 |
| Sample Rate | fSAMP |  |  | 22.3 | ksps | fSCL = 400 kHz (Note 1) | 4 |
| Operating Temperature Range | TA | -40 |  | 125 | °C |  | 4 |
| Extended Temperature Range | TA | -40 |  | 125 | °C |  | 4 |
| Storage Temperature Range | TA | -65 |  | 150 | °C |  | 4 |
| Thermal Resistance, SOT-23 | JA |  | 256 |  | °C/W |  | 4 |
| Supply Voltage (absolute maximum) | VDD |  |  | 7 | V |  | 3 |
| Storage Temperature (absolute maximum) |  | -65 |  | 150 | °C |  | 3 |
| Ambient Temperature with power applied (absolute maximum) |  | -65 |  | 125 | °C |  | 3 |
| Maximum Junction Temperature |  |  |  | 150 | °C |  | 3 |
| ESD protection on all pins |  | 4 |  |  | kV | HBM | 3 |
| Clock Frequency, Standard Mode | fSCL | 0 |  | 100 | kHz |  | 5 |
| Clock High Time, Standard Mode | THIGH | 4000 |  |  | ns |  | 5 |
| Clock Low Time, Standard Mode | TLOW | 4700 |  |  | ns |  | 5 |
| SDA and SCL Rise Time, Standard Mode | TR |  |  | 1000 | ns | From VIL to VIH (Note 1) | 5 |
| SDA and SCL Fall Time, Standard Mode | TF |  |  | 300 | ns | From VIL to VIH (Note 1) | 5 |
| Start Condition Hold Time, Standard Mode | THD:STA | 4000 |  |  | ns |  | 5 |
| Start Condition Setup Time, Standard Mode | TSU:STA | 4700 |  |  | ns |  | 5 |
| Data Input Setup Time, Standard Mode | TSU:DAT | 250 |  |  | ns |  | 5 |
| Stop Condition Setup Time, Standard Mode | TSU:STO | 4000 |  |  | ns |  | 5 |
| Stop Condition Hold Time, Standard Mode | THD:STD | 4000 |  |  | ns |  | 5 |
| Output Valid from Clock, Standard Mode | TAA |  |  | 3500 | ns |  | 5 |
| Bus Free Time, Standard Mode | TBUF | 4700 |  |  | ns | Note 2 | 5 |
| Input Filter Spike Suppression, Standard Mode | TSP |  |  | 50 | ns | SDA and SCL pins (Note 1) | 5 |
| Clock Frequency, Fast Mode | FSCL | 0 |  | 400 | kHz |  | 5 |
| Clock High Time, Fast Mode | THIGH | 600 |  |  | ns |  | 5 |
| Clock Low Time, Fast Mode | TLOW | 1300 |  |  | ns |  | 5 |
| Data Input Hold Time, Fast Mode | THD:DAT | 0 |  | 0.9 | ms |  | 5 |
| Data Input Setup Time, Fast Mode | TSU:DAT | 100 |  |  | ns |  | 5 |
| Output Valid from Clock, Fast Mode | TAA |  |  | 900 | ns |  | 5 |
| Bus Free Time, Fast Mode | TBUF | 1300 |  |  | ns | Note 2 | 5 |
| Input Filter Spike Suppression, Fast Mode | TSP |  |  | 50 | ns | SDA and SCL pins (Note 1) | 5 |

## CAD (KiCad official)

- Symbol: `MCP3221A7T-E`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `mcp3221a7t-e-etched.step` / `mcp3221a7t-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp3221a7t-e.step` / `mcp3221a7t-e.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/mcp3221a7t-e-datasheet.pdf) (30 pp, sha256 `6e11b59a236328b7`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mcp3221a7t-e-datasheet.pdf)