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MCP3201-CI
Public Made by Adomby adom
Microchip Tech Analog To Digital Converters (ADCs), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownMCP3201-CI
Microchip Tech · Analog To Digital Converters (ADCs) · SOIC-8
MCP3201-CI from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Reference voltage input that sets the full-scale range of the on-chip 12-bit SAR DAC. |
| 2 | IN+ | input | Positive analog input that can vary from IN- to VREF + IN-. |
| 3 | IN- | input | Negative analog input that can vary ±100 mV from VSS. |
| 4 | VSS | power_in | Ground reference for the device. |
| 5 | CS/SHDN | input | Chip select/shutdown input: pulled low to initiate communication, and pulled high to end a conversion and enter low-power standby, and it must be pulled high between conversions. |
| 6 | DOUT | output | Serial data output that shifts out A/D conversion results and changes on the falling edge of each clock. |
| 7 | CLK | input | SPI serial clock input used to initiate a conversion and to clock out each bit of the conversion. |
| 8 | VDD | power_in | Power supply input, +2.7V to 5.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Data Converters |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Integral Nonlinearity (MCP3201-C) | INL | -2 | 2 | LSB | MCP3201-C | 3 | |
| Differential Nonlinearity | DNL | -1 | 1 | LSB | No missing codes over temperature | 3 | |
| Gain Error | -5 | 5 | LSB | 3 | |||
| Throughput Rate | fSAMPLE | 100 | ksps | VDD = VREF = 5V | 3 | ||
| Throughput Rate | fSAMPLE | 50 | ksps | VDD = VREF = 2.7V | 3 | ||
| Operating Voltage | VDD | 2.7 | 5.5 | V | 4 | ||
| Operating Current | IDD | 300 | 400 | µA | VDD = 5.0V, DOUT unloaded | 4 | |
| Operating Current | IDD | 210 | µA | VDD = 2.7V, DOUT unloaded | 4 | ||
| Standby Current | IDDS | 0.5 | 2 | µA | CS = VDD = 5.0V | 4 | |
| Clock Frequency | fCLK | 1.6 | MHz | VDD = 5V | 4 | ||
| Clock Frequency | fCLK | 0.8 | MHz | VDD = 2.7V | 4 | ||
| Clock High Time | tHI | 312 | ns | 4 | |||
| Clock Low Time | tLO | 312 | ns | 4 | |||
| CS Fall To First Rising CLK Edge | tSUCS | 100 | ns | 4 | |||
| CS Disable Time | tCSH | 625 | ns | 4 | |||
| CLK Fall To Output Data Valid | tDO | 200 | ns | See Test Circuits, Figure 1-2 | 4 | ||
| CLK Fall To Output Enable | tEN | 200 | ns | See Test Circuits, Figure 1-2 | 4 | ||
| CS Rise To Output Disable | tDIS | 100 | ns | See Test Circuits, Figure 1-2 | 4 | ||
| DOUT Rise Time | tR | 100 | ns | See Test Circuits, Figure 1-2 | 4 | ||
| DOUT Fall Time | tF | 100 | ns | See Test Circuits, Figure 1-2 | 4 | ||
| High Level Output Voltage | VOH | 4.1 | V | IOH = -1 mA, VDD = 4.5V | 4 | ||
| Low Level Output Voltage | VOL | 0.4 | V | IOL = 1 mA, VDD = 4.5V | 4 | ||
| Input Leakage Current | ILI | -10 | 10 | µA | VIN = VSS or VDD | 4 | |
| Output Leakage Current | ILO | -10 | 10 | µA | VOUT = VSS or VDD | 4 | |
| Pin Capacitance (all inputs/outputs) | CIN, COUT | 10 | pF | VDD = 5.0V (Note 1), TA = +25°C, f = 1 MHz | 4 | ||
| Operating Temperature Range | TA | -40 | 85 | °C | 4 | ||
| Storage Temperature Range | TA | -65 | 150 | °C | 4 | ||
| Ambient Temperature with Power Applied | -65 | 125 | °C | 3 | |||
| ESD Protection (HBM) | 4 | kV | All pins | 3 | |||
| Thermal Resistance, 8L-SOIC | θJA | 149.5 | °C/W | 8L-SOIC package | 4 | ||
| Total Harmonic Distortion | THD | -82 | dB | VIN = 0.1V to 4.9V@1 kHz | 3 | ||
| Signal to Noise and Distortion | SINAD | 72 | dB | VIN = 0.1V to 4.9V@1 kHz | 3 | ||
| Spurious Free Dynamic Range | SFDR | 86 | dB | VIN = 0.1V to 4.9V@1 kHz | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead | 37 |
CAD (KiCad official)
- Symbol:
MCP3201-CI - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp3201-ci-etched.step/mcp3201-ci-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp3201-ci.step/mcp3201-ci.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (40 pp, sha256
5b068299258ac365, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).