# MCP3001-I

**Microchip Tech** · Analog To Digital Converters (ADCs) · TSSOP-8

MCP3001-I from Microchip Tech, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Reference voltage input that sets the analog input voltage range and LSB size; it may range from 0.25 V up to VDD. |
| 2 | IN+ | input | Positive analog input that can vary from IN- to VREF + IN-. |
| 3 | IN- | input | Negative analog input that can vary ±100 mV from VSS. |
| 4 | VSS | power_in | Ground reference for the device (VSS = 0 V). |
| 5 | CS/SHDN | input | Chip select/shutdown: pulling low starts communication, and pulling high ends a conversion and puts the device in low-power standby; it must be high between conversions. |
| 6 | DOUT | output | Serial data output that shifts out the A/D conversion result; data changes on the falling edge of each clock. |
| 7 | CLK | input | Serial clock that initiates a conversion and clocks out each bit; clock speed limits apply per Section 6.2 (fCLK up to 2.8 MHz at 5 V, 1.05 MHz at 2.7 V). |
| 8 | VDD | power_in | Power supply input, +2.7 V to 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TSSOP-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD | VDD | 2.7 |  | 5.5 | V |  | 2 |
| Voltage on all inputs and outputs w.r.t. VSS (lower limit) |  | -0.6 |  |  | V |  | 2 |
| ESD protection on all pins (HBM) |  | 4 |  |  | kV | HBM, all pins | 2 |
| Storage temperature | TA | -65 |  | 150 | °C |  | 2 |
| Ambient temperature with power applied | TA | -65 |  | 125 | °C |  | 2 |
| Specified temperature range | TA | -40 |  | 85 | °C |  | 3 |
| Operating temperature range | TA | -40 |  | 85 | °C |  | 3 |
| Active current |  |  |  | 500 | µA | VDD = 5V | 1 |
| Standby current |  |  |  | 2 | µA |  | 1 |
| Throughput rate | fSAMPLE |  |  | 200 | ksps | VDD = VREF = 5V | 2 |
| Throughput rate | fSAMPLE |  |  | 75 | ksps | VDD = VREF = 2.7V | 2 |
| Conversion time | tCONV |  |  | 10 | clock cycles |  | 2 |
| Analog input sample time | tSAMPLE |  | 1.5 |  | clock cycles |  | 2 |
| Integral nonlinearity | INL | -1 | 0.5 | 1 | LSB |  | 2 |
| Differential nonlinearity | DNL | -1 | 0.25 | 1 | LSB | No missing codes over temperature | 2 |
| Offset error |  | -1.5 |  | 1.5 | LSB |  | 2 |
| Gain error |  | -1 |  | 1 | LSB |  | 2 |
| Voltage range (VREF) lower limit | VREF | 0.25 |  |  | V | Note 2 | 2 |
| Current drain (active) | IREF |  | 90 | 150 | µA | CS = VDD = 5V | 2 |
| Current drain | IREF |  | 0.001 | 3 | µA | CS = VDD = 5V | 2 |
| Leakage current |  | -1 | 0.001 | 1 | µA |  | 3 |
| High level output voltage | VOH | 4.1 |  |  | V | IOH = -1 mA, VDD = 4.5V | 3 |
| Low level output voltage | VOL |  |  | 0.4 | V | IOL = 1 mA, VDD = 4.5V | 3 |
| Input leakage current | ILI | -10 |  | 10 | µA | VIN = VSS or VDD | 3 |
| Output leakage current | ILO | -10 |  | 10 | µA | VOUT = VSS or VDD | 3 |
| Pin capacitance (all inputs/outputs) | CIN, COUT |  |  | 10 | pF | VDD = 5.0V (Note 1); TAMB = 25°C, f = 1 MHz | 3 |
| Clock frequency | fCLK |  |  | 2.8 | MHz | VDD = 5V (Note 3) | 3 |
| Clock frequency | fCLK |  |  | 1.05 | MHz | VDD = 2.7V (Note 3) | 3 |
| Clock high time | tHI | 160 |  |  | ns |  | 3 |
| Clock low time | tLO | 160 |  |  | ns |  | 3 |
| CS fall to first rising CLK edge | tSUCS | 100 |  |  | ns |  | 3 |
| CLK fall to output data valid | tDO |  |  | 125 | ns | VDD = 5V, See Figure 1-2 | 3 |
| CLK fall to output data valid | tDO |  |  | 200 | ns | VDD = 2.7, See Figure 1-2 | 3 |
| CLK fall to output enable | tEN |  |  | 125 | ns | VDD = 5V, See Figure 1-2 | 3 |
| CLK fall to output enable | tEN |  |  | 200 | ns | VDD = 2.7, See Figure 1-2 | 3 |
| CS rise to output disable | tDIS |  |  | 100 | ns | See test circuits, Figure 1-2 (Note 1) | 3 |
| CS disable time | tCSH | 350 |  |  | ns |  | 3 |
| DOUT rise time | tR |  |  | 100 | ns | See test circuits, Figure 1-2 (Note 1) | 3 |
| DOUT fall time | tF |  |  | 100 | ns | See test circuits, Figure 1-2 (Note 1) | 3 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | 8-Lead Plastic Small Outline (SN), Narrow, 3.90 mm Body [SOIC] Notes: | 20 |

## CAD (KiCad official)

- Symbol: `MCP3001-I`
- Footprint: `Package_SO:TSSOP-8_4.4x3mm_P0.65mm`
- 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `mcp3001-i-etched.step` / `mcp3001-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp3001-i.step` / `mcp3001-i.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/mcp3001-i-datasheet.pdf) (28 pp, sha256 `e33e0aa1aab97a02`, retrieved 2026-11-06, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mcp3001-i-datasheet.pdf)