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MCP25625T-E

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Microchip Tech CAN Transceivers, QFN-28-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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MCP25625T-E

Microchip Tech · CAN Transceivers · QFN-28-EP(6x6)

MCP25625T-E from Microchip Tech, in a QFN-28-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input SPI Chip Select input for the CAN controller interface.
2 RESET input Hardware Reset input; a low level resets the device, and an RC network can hold it in Reset for at least 2 µs after VDD reaches its operating voltage.
3 VDD power_in Power supply for the CAN controller, 2.7 V to 5.5 V.
4 TxCAN output Transmit output from the CAN controller to the TXD input of the CAN transceiver.
5 RXCAN input Receive input from the CAN transceiver RXD output.
6 CLKOUT output Clock output (also SOF) with internal prescaler dividing FOSC by 1, 2, 4 or 8, 25 MHz maximum, high-impedance when disabled.
7 Tx0RTS input Request-to-send input for transmit buffer TXB0; can be configured as a general purpose I/O.
8 Tx1RTS input Request-to-send input for transmit buffer TXB1; can be configured as a general purpose I/O.
9 Tx2RTS input Request-to-send input for transmit buffer TXB2; can be configured as a general purpose I/O.
10 RXD output CMOS-compatible receive data output from the CAN transceiver, supplied by VIO; high when the bus is recessive and low when dominant.
11 VIO power_in Supply for the CAN transceiver digital I/O pins, digital supply range 2.7 V to 5.5 V.
12 CANL bidirectional CAN low-level high-voltage I/O; disconnected from the bus when VDDA is not powered.
13 CANH bidirectional CAN high-level high-voltage I/O; disconnected from the bus when VDDA is not powered.
14 NC unconnected No connection.
15 STBY input Standby mode input selecting Normal or Standby mode of the CAN transceiver; internally pulled up to VIO.
16 TXD input Transmit data input from the CAN controller; low drives the bus dominant, with an internal pull-up of nominal 33 kΩ to VIO.
17 NC unconnected No connection.
18 VSS power_in Ground supply pin for the CAN transceiver.
19 VDDA power_in Positive supply for the CAN transceiver and wake-up receiver, 4.5 V to 5.5 V.
20 OSC2 output Crystal/ceramic resonator output for the internal oscillator (parallel cut crystal required).
21 OSC1 input Crystal/ceramic resonator input, or external clock input to the oscillator.
22 GND power_in Ground for the CAN controller.
23 Rx1BF output RxB1 buffer-full output; can be configured as an interrupt pin or general purpose output.
24 Rx0BF output RxB0 buffer-full output; can be configured as an interrupt pin or general purpose output.
25 INT output Interrupt output to the microcontroller; interrupts are cleared through SPI.
26 SCK input SPI clock input, up to 10 MHz.
27 SI input SPI data input.
28 SO output SPI data output.
29 EP passive Exposed thermal pad; recommended to connect to VSS to enhance electromagnetic immunity and thermal resistance.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-28-EP(6x6)
Category Interface
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD VDD 7 V 67
Supply Voltage VDDA VDDA 7 V 67
Supply Voltage VIO VIO 7 V 67
DC Voltage at CANH, CANL -58 58 V 67
DC Voltage at TXD, RXD, STBY w.r.t VSS -0.3 V max VIO + 0.3 V 67
DC Voltage at All Other I/Os w.r.t GND -0.3 V max VDD + 0.3 V 67
Transient Voltage on CANH, CANL (ISO-7637) -150 100 V ISO-7637 Figure 7-5 67
Storage temperature -55 150 °C 67
Operating Ambient Temperature -40 125 °C 67
Virtual Junction Temperature (IEC60747-1) TVJ -40 150 °C 67
Soldering Temperature of Leads (10 seconds) 300 °C 67
VDD Supply Voltage VDD 2.7 5.5 V 68
Register Retention Voltage VRET 2.4 V 68
Low-Level Input Voltage RxCAN, TxnRTS (VIL) VIL -0.3 V 68
Low-Level Input Voltage SCK, CS, SI (VIL) VIL -0.3 V 68
Low-Level Output Voltage TxCAN VOL 0.6 V IOL = +6.0 mA, VDD = 4.5V 68
Low-Level Output Voltage RxnBF Pins VOL 0.6 V IOL = +8.5 mA, VDD = 4.5V 68
Low-Level Output Voltage SO, CLKOUT VOL 0.6 V IOL = +2.1 mA, VDD = 4.5V 68
Low-Level Output Voltage INT VOL 0.6 V IOL = +1.6 mA, VDD = 4.5V 68
Input Leakage Current, All I/Os except OSC1 and TxnRTS Pins ILI -1 1 µA CS = RESET = VDD, VIN = VSS to VDD 68
Input Leakage Current, OSC1 Pin ILI -5 5 µA 68
Internal Capacitance (all inputs and outputs) CINT 7 pF TAMB = +25°C, fC = 1.0 MHz, VDD = 0V 68
Operating Current IDD 10 mA VDD = 5.5V, FOSC = 25 MHz, FCLK = 1 MHz, SO = Open 68
Standby Current (Sleep mode) IDDS 8 µA CS, TxnRTS = VDD, Inputs tied to VDD or VSS, -40°C to +125°C 68
Clock In Frequency FOSC 1 25 MHz 68
Clock In Period TOSC 40 1000 ns 68
Duty Cycle (External Clock input) tDUTY 0.45 0.55 , TOSH/(TOSH + TOSL) 68
Wake-up Noise Filter tWF 100 ns 69
RESET Pin Low Time tRL 2 µs 69
Clock Frequency (SPI) FCLK 10 MHz 70
Data Setup Time tSU 10 ns 70
Supply Voltage Range VDDA VDDA 4.5 5.5 V 71
Supply Current VDDA (Recessive) IDD 5 10 mA Recessive; VTXD = VDDA 71
Supply Current VDDA (Dominant) IDD 45 70 mA Dominant; VTXD = 0V 71
Standby Current VDDA IDDS 5 15 µA Includes IIO 71
High Level of the POR Comparator VPORH 3.8 4.3 V 71
Low Level of the POR Comparator VPORL 3.4 4 V 71
Hysteresis of POR Comparator VPORD 0.3 0.8 V 71
Digital Supply Voltage Range VIO VIO 2.7 5.5 V 71
Supply Current on VIO (Recessive) IIO 4 30 µA Recessive; VTXD = VIO 71
Supply Current on VIO (Dominant) IIO 85 500 µA Dominant; VTXD = 0V 71
Standby Current VIO IDDS 0.3 1 µA 71
CANH, CANL: Recessive Bus Output Voltage VO(R) 2 3 V VTXD = VDDA; No load 71
CANH, CANL: Bus Output Voltage in Standby VO(S) -0.1 0 0.1 V STBY = VTXD = VDDA; No load 71
Recessive Output Current IO(R) -5 5 mA -24V < VCAN < +24V 71
CANH: Dominant Output Voltage VO(D) 2.75 3.5 4.5 V TXD = 0; RL = 50 to 65 71
CANL: Dominant Output Voltage VO(D) 0.5 1.5 2.25 V RL = 50 to 65 71
Symmetry of Dominant Output Voltage (VDD, VCANH, VCANL) VO(D)(M) -400 0 400 mV VTXD = VSS 71
Dominant: Differential Output Voltage VO(DIFF) 1.5 2 3 V VTXD = VSS; RL = 50 to 65 71
Recessive: Differential Output Voltage VO(DIFF) -120 0 12 mV VTXD = VDDA 71
Recessive Differential Input Voltage VDIFF(R)(I) -1 0.5 V Normal mode; -12V < V(CANH, CANL) < +12V 72
Dominant Differential Input Voltage VDIFF(D)(I) 0.9 V Normal mode; -12V < V(CANH, CANL) < +12V 72
Differential Receiver Threshold VTH(DIFF) 0.5 0.7 0.9 V Normal mode; -12V < V(CANH, CANL) < +12V 72
Differential Input Hysteresis VHYS(DIFF) 50 200 mV Normal mode; see Figure 7-6 72
Common-Mode Input Resistance RIN 10 30 k 72
Shutdown Junction Temperature TJ(SD) 165 175 185 °C -12V < V(CANH, CANL) < +12V 72
Shutdown Temperature Hysteresis TJ(HYST) 20 30 °C -12V < V(CANH, CANL) < +12V 72
Operating Temperature Range TA -40 125 °C 77
Storage Temperature Range TA -65 150 °C 77
Thermal Resistance, 28L-QFN 6x6 mm JA 32.8 C/W 77

CAD (KiCad official)

  • Symbol: MCP25625T-E
  • Footprint: Package_DFN_QFN:QFN-28-1EP_6x6mm_P0.65mm_EP4.8x4.8mm
  • 3D model: QFN-28-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: mcp25625t-e-etched.step / mcp25625t-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp25625t-e.step / mcp25625t-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (90 pp, sha256 b668c3cd8762638d, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF