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MCP2558FDT-H

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Microchip Tech CAN Transceivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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MCP2558FDT-H

Microchip Tech · CAN Transceivers · SOIC-8

MCP2558FDT-H from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXD input Transmit data input: Low drives CANH/CANL dominant and High leaves them recessive, with an internal pull-up (nominal 33 kΩ) to VIO on the MCP2558FD.
2 VSS power_in Ground supply pin.
3 VDD power_in Positive supply voltage pin that supplies the transmitter and receiver.
4 RXD output CMOS-compatible receive data output that is High when the CAN bus is recessive and Low when dominant, driven to the VIO level on the MCP2558FD.
5 VIO power_in Digital I/O supply pin for TXD, RXD and S on the MCP2558FD, supporting MCU I/O ranges from 1.8 V to 5 V; the device is unpowered if VIO drops below the POR level.
6 CANL bidirectional CAN low-level voltage I/O that drives the low side of the CAN differential bus and disconnects from the bus when the device is not powered.
7 CANH bidirectional CAN high-level voltage I/O that drives the high side of the CAN differential bus and disconnects from the bus when the device is not powered.
8 S input Silent mode input that selects Silent mode (transmitter off, high-speed receiver active) when high; it has an internal MOS pull-up to VIO whose value depends on supply (typically 660 kΩ at 5 V, 1.1 MΩ at 3.3 V, 4.4 MΩ at 1.8 V).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD VDD 7 V 10
Supply voltage VIO VIO 7 V 10
DC voltage at TXD, RXD, S and VSS -0.3 V Upper limit printed as VIO + 0.3 V 10
DC voltage at CANH and CANL -58 58 V 10
Transient voltage on CANH and CANL -150 100 V ISO/DIS-7637 (Figure 2-5) 10
Differential bus input voltage VDIFF(I) -5 10 V t = 60 days, continuous 10
Differential bus input voltage (pulses) VDIFF(I) 17 V 1000 pulses, t = 0.1 ms, VCANH = +18V 10
Dominant state detection VDIFF(I) VDIFF(I) 9 V 10000 pulses, t = 1 ms 10
Storage temperature -55 150 °C 10
Operating ambient temperature -40 150 °C 10
Virtual junction temperature TVJ TVJ -40 190 °C IEC60747-1 10
Soldering temperature of leads 300 °C 10 seconds 10
ESD protection on CANH and CANL pins -13 13 kV IEC 61000-4-2 10
ESD protection on CANH and CANL pins -8 8 kV IEC 801; Human Body Model 10
ESD protection on all other pins -4 4 kV IEC 801; Human Body Model 10
ESD protection on all pins -400 400 V IEC 801; Machine Model 10
ESD protection on all pins -750 750 V IEC 801; Charge Device Model 10
Specified temperature range TA -40 150 °C 19
Operating temperature range TA -40 150 °C 19
Storage temperature range TA -65 155 °C 19
Voltage range VDD (VDD pin) VDD 4.5 5.5 V 11
Supply current IDD 2.5 5 mA Recessive; VTXD = VDD 11
Supply current (dominant) IDD 55 70 mA Dominant; VTXD = 0V 11
Silent current IDDS 1 3 mA MCP2558FD; includes IIO 11
Maximum supply current IDDMAX 95 140 mA Fault condition: VTXD = VSS; VCANH = VCANL = -5V to +18V 11
High level of the UV comparator for VDD VUVH 4 4.25 4.4 V 11
Low level of the UV comparator for VDD VUVL 3.6 3.8 4 V 11
Digital supply voltage range VIO VIO 1.7 5.5 V 11
CANH: Dominant output voltage VO(D) 2.75 3.5 4.5 V TXD = 0; RL = 50 to 65 11
CANL: Dominant output voltage VO(D) 0.5 1.5 2.25 V RL = 50 to 65 11
Dominant differential output voltage VO(DIFF)(D) 1.5 2 3 V VTXD = VSS; RL = 50 to 65 (Note 1) 12
Recessive differential output voltage VO(DIFF)(R) -500 0 50 mV VTXD = VDD, no load 12
Recessive differential input voltage VDIFF(R)(I) -4 0.5 V -12V < V(CANH, CANL) < +12V; see Figure 2-6 (Note 3) 12
Dominant differential input voltage VDIFF(D)(I) 0.9 9 V -12V < V(CANH, CANL) < +12V; see Figure 2-6 (Note 3) 12
Differential receiver threshold VTH(DIFF) 0.5 0.7 0.9 V -12V < V(CANH, CANL) < +12V; see Figure 2-6 (Note 3) 12
Differential input hysteresis VHYS(DIFF) 30 200 mV See Figure 2-6, (Note 1) 12
Differential input resistance RDIFF 12 25 100 k Note 1 12
CANH, CANL: input leakage ILI -5 5 µA VDD = VTXD = VS = 0V. For MCP2558FD, VIO = 0V. VCANH = VCANL = 5 V. 12
TXD: low-level input current IIL(TXD) -270 -150 -30 µA 13
S: low-level input current IIL(S) -30 -1 µA 13
Low-level output voltage (RXD) VOL 0.4 V IOL = 4 mA; typical 8 mA 13
Shutdown junction temperature TJ(SD) 165 175 185 °C -12V < V(CANH, CANL) < +12V (Note 1) 13
Bit time tBIT 0.125 69.44 µs 14
Nominal bit rate NBR 14.4 8000 kbps 14
Delay TXD low to bus dominant tTXD-BUSON 50 85 ns Note 1 14
Delay TXD high to bus recessive tTXD-BUSOFF 40 85 ns Note 1 14
Delay bus dominant to RXD tBUSON-RXD 70 85 ns Note 1 14
Delay bus recessive to RXD tBUSOFF-RXD 110 145 ns Note 1 14
Propagation delay TXD to RXD tTXD-RXD 90 120 ns Worst case of tLOOP(R) and tLOOP(F) Figure 2-9 15
Propagation delay, rising edge tLOOP(R) 90 120 ns 15
Propagation delay, falling edge tLOOP(F) 80 120 ns 15
Recessive bit time on RXD, 2 Mbps loop delay symmetry tBIT(RXD), 2M 450 490 550 ns tBIT(TXD) = 500 ns (Figure 2-9) 15
Recessive bit time on RXD, 5 Mbps loop delay symmetry tBIT(RXD), 5M 160 190 220 ns tBIT(TXD) = 200 ns (Figure 2-9) 15
Recessive bit time on RXD, 8 Mbps loop delay symmetry tBIT(RXD), 8M 85 100 135 ns tBIT(TXD) = 120 ns (Figure 2-9) (Note 1) 15
Delay silent to normal mode tWAKE 7 30 µs Negative edge on S 15
Permanent dominant detect time tPDT 0.8 1.9 5 ms TXD = 0V 15
Transmitted bit time on bus, 5 Mbps tBIT(BUS), 5M 155 200 210 ns tBIT(TXD) = 200 ns (Figure 2-9) (Note 1) 16
Transmitted bit time on bus, 8 Mbps tBIT(BUS), 8M 100 125 140 ns tBIT(TXD) = 120 ns (Figure 2-9) (Note 1) 16
Receiver timing symmetry, 5 Mbps tDIFF(REC),5M -45 0 15 ns tBIT(TXD) = 200 ns (Figure 2-9) (Note 1) 16
Thermal resistance, 8LD SOIC JA 149.5 °C/W 19

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin b) MCP2557FD-H/SN: 8-lead, Plastic Small Outline SOIC pack￾age. 33

CAD (KiCad official)

  • Symbol: MCP2558FDT-H
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: mcp2558fdt-h-etched.step / mcp2558fdt-h-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp2558fdt-h.step / mcp2558fdt-h.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (36 pp, sha256 cf1d404e4b3aaf8a, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF