component
MCP2558FD-H
Public Made by Adomby adom
Microchip Tech CAN Transceivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownMCP2558FD-H
Microchip Tech · CAN Transceivers · SOIC-8
MCP2558FD-H from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TXD | input | Transmit data input that drives CANH/CANL dominant when Low and recessive when High, with an internal pull-up of nominal 33 kΩ to VIO on the MCP2558FD. |
| 2 | VSS | power_in | Ground supply pin. |
| 3 | VDD | power_in | Positive supply voltage pin that supplies the transmitter and receiver. |
| 4 | RXD | output | CMOS-compatible receive data output that is High when the bus is recessive and Low when dominant, driven to VIO on the MCP2558FD. |
| 5 | VIO | power_in | Digital I/O supply pin for TXD, RXD and S, which provides the internal level shifter on the MCP2558FD. |
| 6 | CANL | bidirectional | CAN low-level voltage I/O that drives the low side of the CAN differential bus and disconnects from the bus when the device is unpowered. |
| 7 | CANH | bidirectional | CAN high-level voltage I/O that drives the high side of the CAN differential bus and disconnects from the bus when the device is unpowered. |
| 8 | S | input | Silent mode input that sets Normal or Silent mode, where in Silent mode the transmitter is off and the high-speed receiver stays active, with an internal MOS pull-up to VIO (typically 660 kΩ at 5 V, 1.1 MΩ at 3.3 V, 4.4 MΩ at 1.8 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Interface |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD Pin Voltage Range | VDD | 4.5 | 5.5 | V | 11 | ||
| Supply Current (Recessive) | IDD | 2.5 | 5 | mA | Recessive; VTXD = VDD | 11 | |
| Supply Current (Dominant) | IDD | 55 | 70 | mA | Dominant; VTXD = 0V | 11 | |
| Silent Current | IDDS | 1 | 3 | mA | MCP2558FD; includes IIO | 11 | |
| Maximum Supply Current | IDDMAX | 95 | 140 | mA | Fault condition: VTXD = VSS; VCANH = VCANL = -5V to +18V | 11 | |
| High Level of the POR Comparator for VDD | VPORH | 3 | 3.95 | V | Note 1 (characterized; not 100% tested) | 11 | |
| Low Level of the POR Comparator for VDD | VPORL | 1 | 2 | 3.2 | V | Note 1 (characterized; not 100% tested) | 11 |
| Hysteresis of POR Comparator for VDD | VPORD | 0.2 | 0.9 | 2 | V | Note 1 (characterized; not 100% tested) | 11 |
| High Level of the UV Comparator for VDD | VUVH | 4 | 4.25 | 4.4 | V | 11 | |
| Low Level of the UV Comparator for VDD | VUVL | 3.6 | 3.8 | 4 | V | 11 | |
| Digital Supply Voltage Range (VIO pin) | VIO | 1.7 | 5.5 | V | 11 | ||
| Supply Current on VIO (Recessive) | IIO | 7 | 30 | µA | Recessive; VTXD = VIO | 11 | |
| Supply Current on VIO (Dominant) | IIO | 200 | 400 | µA | Dominant; VTXD = 0V | 11 | |
| High Level of the POR Comparator for VIO | VPORH_VIO | 0.8 | 1.2 | 1.7 | V | 11 | |
| Low Level of the POR Comparator for VIO | VPORL_VIO | 0.7 | 1.1 | 1.4 | V | 11 | |
| CANH; CANL: Recessive Bus Output Voltage | VO(R) | 2 | 3 | V | VTXD = VDD; No load | 11 | |
| Recessive Output Current | IO(R) | -5 | 5 | mA | -24V < VCAN < +24V | 11 | |
| CANH: Dominant Output Voltage | VO(D) | 2.75 | 3.5 | 4.5 | V | TXD = 0; RL = 50 to 65 | 11 |
| CANL: Dominant Output Voltage | 0.5 | 1.5 | 2.25 | V | RL = 50 to 65 | 11 | |
| Driver Symmetry (VCANH+VCANL)/VDD | VSYM | 0.9 | 1 | 1.1 | V | 1 MHz square wave, Recessive and Dominant states, and transition (Note 1) | 11 |
| Dominant Differential Output Voltage | VO(DIFF)(D) | 1.5 | 2 | 3 | V | VTXD = VSS; RL = 50 to 65 (Note 1) | 12 |
| Dominant Differential Output Voltage | VO(DIFF)(D) | 1.4 | 2 | 3 | V | VTXD = VSS; RL = 45 to 70 (Note 1) | 12 |
| Dominant Differential Output Voltage | VO(DIFF)(D) | 1.3 | 2 | 3 | V | VTXD = VSS; RL = 40 to 75 | 12 |
| Dominant Differential Output Voltage | VO(DIFF)(D) | 1.5 | 5 | V | VTXD = VSS; RL = 2240 (as printed) | 12 | |
| Recessive: Differential Output Voltage | VO(DIFF)(R) | -500 | 0 | 50 | mV | VTXD = VDD, no load | 12 |
| CANH: Short-Circuit Output Current | IO(SC) | -115 | -85 | mA | VTXD = VSS; VCANH = -3V; CANL floating | 12 | |
| CANL: Short Circuit Output Current | 75 | 115 | mA | VTXD = VSS; VCANL = +18V; CANH floating | 12 | ||
| Recessive Differential Input Voltage | VDIFF(R)(I) | -4 | 0.5 | V | -12V < V(CANH, CANL) < +12V; see Figure 2-6 (Note 3) | 12 | |
| Dominant Differential Input Voltage | VDIFF(D)(I) | 0.9 | 9 | V | -12V < V(CANH, CANL) < +12V; see Figure 2-6 (Note 3) | 12 | |
| Differential Receiver Threshold | VTH(DIFF) | 0.5 | 0.7 | 0.9 | V | -12V < V(CANH, CANL) < +12V; see Figure 2-6 (Note 3) | 12 |
| Differential Input Hysteresis | VHYS(DIFF) | 30 | 200 | mV | See Figure 2-6 (Note 1) | 12 | |
| Single Ended Input Resistance | RCAN_H, RCAN_L | 6 | 50 | k | Note 1 | 12 | |
| Internal Resistance Matching | mR | -3 | 0 | 3 | % | VCANH = VCANL (Note 1) | 12 |
| Differential Input Resistance | RDIFF | 12 | 25 | 100 | k | Note 1 | 12 |
| CANH, CANL: Input Leakage | ILI | -5 | 5 | µA | VDD = VTXD = VS = 0V; for MCP2558FD VIO = 0V; VCANH = VCANL = 5 V | 12 | |
| Low-Level Input Voltage (MCP2558FD) | VIL | -0.3 | V | MCP2558FD | 13 | ||
| High-Level Input Current | IIH | -1 | 1 | µA | 13 | ||
| TXD: Low-Level Input Current | IIL(TXD) | -270 | -150 | -30 | µA | 13 | |
| S: Low-Level Input Current | IIL(S) | -30 | -1 | µA | 13 | ||
| Low-Level Output Voltage | VOL | 0.4 | V | IOL = 4 mA; typical 8 mA | 13 | ||
| Shutdown Junction Temperature | TJ(SD) | 165 | 175 | 185 | °C | -12V < V(CANH, CANL) < +12V (Note 1) | 13 |
| Shutdown Temperature Hysteresis | TJ(HYST) | 15 | 30 | °C | -12V < V(CANH, CANL) < +12V (Note 1) | 13 | |
| Nominal Bit Rate | NBR | 14.4 | 8000 | kbps | 14 | ||
| Delay TXD Low to Bus Dominant | tTXD-BUSON | 50 | 85 | ns | Note 1 (characterized, not 100% tested) | 14 | |
| Delay TXD High to Bus Recessive | tTXD-BUSOFF | 40 | 85 | ns | Note 1 (characterized, not 100% tested) | 14 | |
| Delay Bus Dominant to RXD | tBUSON-RXD | 70 | 85 | ns | Note 1 (characterized, not 100% tested) | 14 | |
| Delay Bus Recessive to RXD | tBUSOFF-RXD | 110 | 145 | ns | Note 1 (characterized, not 100% tested) | 14 | |
| Propagation Delay TXD to RXD | tTXD - RXD | 90 | 120 | ns | Worst case of tLOOP(R) and tLOOP(F), Figure 2-9 | 15 | |
| Delay Silent to Normal Mode | tWAKE | 7 | 30 | µs | Negative edge on S | 15 | |
| Permanent Dominant Detect Time | tPDT | 0.8 | 1.9 | 5 | ms | TXD = 0V | 15 |
| VDD Supply Voltage (Absolute Maximum) | VDD | 7 | V | 10 | |||
| VIO Supply Voltage (Absolute Maximum) | VIO | 7 | V | 10 | |||
| DC Voltage at TXD, RXD, S and VSS | -0.3 | V | 10 | ||||
| DC Voltage at CANH and CANL | -58 | 58 | V | 10 | |||
| Transient Voltage on CANH and CANL (ISO/DIS-7637) | -150 | 100 | V | ISO/DIS-7637 (Figure 2-5) | 10 | ||
| Differential Bus Input Voltage VDIFF(I) | VDIFF(I) | -5 | 10 | V | t = 60 days, continuous | 10 | |
| Differential Bus Input Voltage VDIFF(I) | VDIFF(I) | 17 | V | 1000 pulses, t = 0.1 ms, VCANH = +18V | 10 | ||
| Operating Temperature Range | TA | -40 | 150 | °C | 19 | ||
| Storage Temperature Range | TA | -65 | 155 | °C | 19 | ||
| Thermal Resistance, 8LD SOIC | JA | 149.5 | C/W | 19 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | b) MCP2557FD-H/SN: 8-lead, Plastic Small Outline SOIC package. | 33 |
CAD (KiCad official)
- Symbol:
MCP2558FD-H - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp2558fd-h-etched.step/mcp2558fd-h-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp2558fd-h.step/mcp2558fd-h.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (36 pp, sha256
cf1d404e4b3aaf8a, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).